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KMM466S823DT2-F0 PDF预览

KMM466S823DT2-F0

更新时间: 2024-11-25 21:10:11
品牌 Logo 应用领域
三星 - SAMSUNG 时钟动态存储器内存集成电路
页数 文件大小 规格书
10页 141K
描述
Synchronous DRAM Module, 8MX64, 7ns, CMOS, SODIMM-144

KMM466S823DT2-F0 技术参数

生命周期:Obsolete零件包装代码:MODULE
包装说明:DIMM, DIMM144,32针数:144
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.28风险等级:5.84
访问模式:FOUR BANK PAGE BURST最长访问时间:7 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N144
内存密度:536870912 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:144
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM144,32
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:3.3 V认证状态:Not Qualified
刷新周期:4096座面最大高度:29.21 mm
自我刷新:YES最大待机电流:0.008 A
子类别:DRAMs最大压摆率:1 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:0.8 mm
端子位置:DUALBase Number Matches:1

KMM466S823DT2-F0 数据手册

 浏览型号KMM466S823DT2-F0的Datasheet PDF文件第2页浏览型号KMM466S823DT2-F0的Datasheet PDF文件第3页浏览型号KMM466S823DT2-F0的Datasheet PDF文件第4页浏览型号KMM466S823DT2-F0的Datasheet PDF文件第5页浏览型号KMM466S823DT2-F0的Datasheet PDF文件第6页浏览型号KMM466S823DT2-F0的Datasheet PDF文件第7页 
KMM466S823DT2  
PC66 SODIMM  
Revision History  
Revision 0.0 (July 5, 1999)  
• Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.  
• Skip ICC4 value of CL=2 in DC characteristics in datasheet.  
• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.  
• Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.  
• Symbol Change Notice  
Before  
After  
I
I
I
Input leakage current (inputs)  
IL  
I
Input leakage current  
LI  
Input leakage current (I/O pins)  
IL  
Output open @ DC characteristic table  
Io  
Output open @ DC characteristic table  
OL  
Test Condition in DC CHARACTERISTIC Change Notice  
Symbol  
Before  
CKE £ VIL(max), tCC = 15ns  
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns  
After  
I
I
I
CKE £ VIL(max), tCC = 10ns  
CC2P , CC3P  
I
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns  
CC2N , CC3N  
Input signals are changed one time during 30ns  
Input signals are changed one time during 20ns  
I
2 Banks activated  
4 Banks activated  
CC4  
• Added Notes @OPERATING AC PARAMETER  
Notes : 5. For -0, tRDL=1CLK and tDAL=1CLK+20ns is also supported .  
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.  
Revision 0.1 (July 29, 1999)  
• Changed misprinted "Detail Y" @ PACKAGE DIMENSIONS.  
REV. 0.1 July 1999  

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