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KM684002CIJ-15 PDF预览

KM684002CIJ-15

更新时间: 2024-01-20 19:17:33
品牌 Logo 应用领域
三星 - SAMSUNG 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 182K
描述
Standard SRAM, 512KX8, 15ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36

KM684002CIJ-15 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ,针数:36
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.83
Is Samacsys:N最长访问时间:15 ns
JESD-30 代码:R-PDSO-J36长度:23.5 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:36字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:3.76 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

KM684002CIJ-15 数据手册

 浏览型号KM684002CIJ-15的Datasheet PDF文件第2页浏览型号KM684002CIJ-15的Datasheet PDF文件第3页浏览型号KM684002CIJ-15的Datasheet PDF文件第4页浏览型号KM684002CIJ-15的Datasheet PDF文件第6页浏览型号KM684002CIJ-15的Datasheet PDF文件第7页浏览型号KM684002CIJ-15的Datasheet PDF文件第8页 
PRELIMINARY  
Preliminary  
CMOS SRAM  
KM684002C, KM684002CI  
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)  
TEST CONDITIONS*  
Parameter  
Value  
Input Pulse Levels  
0V to 3V  
3ns  
Input Rise and Fall Times  
Input and Output timing Reference Levels  
Output Loads  
1.5V  
See below  
* The above test conditions are also applied at industrial temperature range.  
Output Loads(A)  
Output Loads(B)  
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ  
+5.0V  
RL = 50W  
DOUT  
VL = 1.5V  
30pF*  
480W  
DOUT  
ZO = 50W  
255W  
5pF*  
* Including Scope and Jig Capacitance  
* Capacitive Load consists of all components of the  
test environment.  
READ CYCLE*  
KM684002C-12  
KM684002C-15  
KM684002C-20  
Parameter  
Symbol  
Unit  
Min  
12  
-
Max  
Min  
15  
-
Max  
Min  
20  
-
Max  
Read Cycle Time  
tRC  
tAA  
-
12  
12  
6
-
15  
15  
7
-
20  
20  
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
tLZ  
-
-
-
Output Enable to Valid Output  
Chip Enable to Low-Z Output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Chip Selection to Power Up Time  
Chip Selection to Power DownTime  
-
-
-
3
-
3
-
3
-
tOLZ  
tHZ  
0
-
0
-
0
-
0
6
0
7
0
9
tOHZ  
tOH  
tPU  
tPD  
0
6
0
7
0
9
3
-
3
-
3
-
0
-
0
-
0
-
-
12  
-
15  
-
20  
* The above parameters are also guaranteed at industrial temperature range.  
Rev 2.0  
August 1999  
- 5 -  

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SRAM