Datasheet > KM48V512DJ-L7

KM48V512DJ-L7

更新时间： 2024-11-03 07:23:27

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器光电二极管
页数	文件大小	规格书
20页	365K
描述
Fast Page DRAM, 512KX8, 70ns, CMOS, PDSO28, 0.400 INCH, SOJ-28

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中文翻译

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数据手册

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KM48V512DJ-L7 数据手册

KM48C512D, KM48V512D

CMOS DRAM

512K x 8Bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

This is a family of 524,288 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells

within the same row. Power supply voltage(+5.0V or +3.3V), Access time(-5,-6,-7), power consumption(Normal or Low power) and

package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and

Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 512Kx8 Fast Page Mode DRAM family is

fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.

It may be used as main memory unit for microcomputer, personal computer and portable machines.

•

Fast Page Mode operation

Byte Read/Write operation

FEATURES

CAS-before-RAS refresh capability

•

Part Identification

• RAS-only and Hidden refresh capability

• Self-refresh capability (L-ver only)

- KM48C512D/DL (5V, 1K Ref.)

- KM48V512D/DL (3.3V, 1K Ref.)

• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

•

Active Power Dissipation

•

JEDEC Standard pinout

Unit : mW

5V (1K Ref.)

Available in 28-pin SOJ 400mil & TSOP(II) 400mil

packages

Speed

-5

3.3V (1K Ref.)

470

385

360

• Dual +5V±10% power supply(5V product)

• Dual +3.3V±0.3V power supply(3.3V product)

-6

255

235

-7

•

Refresh Cycles

FUNCTIONAL BLOCK DIAGRAM

Part

VCC

Refresh

cycle

Refresh period

NO.

RAS

CAS

Normal

L-ver

Vcc

Vss

Control

Clocks

C512D

VBB Generator

16ms

128ms

V512D 3.3V

Data in

Buffer

Row Decoder

Refresh Timer

Refresh Control

•

Performance Range

Speed

Remark

5V Only

5V/3.3V

tRAC

50ns

60ns

70ns

tCAC

tRC

tPC

35ns

DQ0

DQ7

Memory Array

524,288 x8

Cells

-5

-6

-7

15ns

90ns

Refresh Counter

Row Address Buffer

Col. Address Buffer

15ns 110ns 40ns

20ns 130ns 45ns

A0 - A9

A0 - A8

Data out

Buffer

Column Decoder

SAMSUNG ELECTRONICS CO., LTD. reserves the right to

change products and specifications without notice.

12 3 4 5 6 7...20

中文翻译

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与KM48V512DJ-L7相关器件

型号	品牌	获取价格	描述	数据表
KM48V512DLT-7	SAMSUNG	获取价格	Fast Page DRAM, 512KX8, 70ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, TSOP2-28
KM48V512DT-6	SAMSUNG	获取价格	Fast Page DRAM, 512KX8, 60ns, CMOS, PDSO28, 0.400 INCH, TSOP2-28
KM48V512DT-L6	SAMSUNG	获取价格	Fast Page DRAM, 512KX8, 60ns, CMOS, PDSO28, 0.400 INCH, TSOP2-28
KM48V514BJ-7	SAMSUNG	获取价格	EDO DRAM, 512KX8, 70ns, CMOS, PDSO28, 0.400 INCH, SOJ-28
KM48V514BJ-8	SAMSUNG	获取价格	EDO DRAM, 512KX8, 80ns, CMOS, PDSO28, 0.400 INCH, SOJ-28
KM48V514BJ-L6	SAMSUNG	获取价格	EDO DRAM, 512KX8, 60ns, CMOS, PDSO28, 0.400 INCH, SOJ-28
KM48V514BJ-L8	SAMSUNG	获取价格	EDO DRAM, 512KX8, 80ns, CMOS, PDSO28, 0.400 INCH, SOJ-28
KM48V514BLLJ-6	SAMSUNG	获取价格	EDO DRAM, 512KX8, 60ns, CMOS, PDSO28, PLASTIC, SOJ-28
KM48V514BLLJ-7	SAMSUNG	获取价格	EDO DRAM, 512KX8, 70ns, CMOS, PDSO28, PLASTIC, SOJ-28
KM48V514BLLJ-8	SAMSUNG	获取价格	EDO DRAM, 512KX8, 80ns, CMOS, PDSO28, PLASTIC, SOJ-28

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