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KM44V1004DJ-L7 PDF预览

KM44V1004DJ-L7

更新时间: 2024-11-01 18:15:23
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
22页 413K
描述
EDO DRAM, 1MX4, 70ns, CMOS, PDSO20, 0.300 INCH, SOJ-26/20

KM44V1004DJ-L7 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:SOJ, SOJ20/26,.34
针数:20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.92访问模式:FAST PAGE WITH EDO
最长访问时间:70 ns其他特性:CAS BEFORE RAS/RAS ONLY/HIDDEN/SELF REFRESH
I/O 类型:COMMONJESD-30 代码:R-PDSO-J20
JESD-609代码:e0长度:17.15 mm
内存密度:4194304 bit内存集成电路类型:EDO DRAM
内存宽度:4功能数量:1
端口数量:1端子数量:20
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX4
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ20/26,.34
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified刷新周期:1024
座面最大高度:3.76 mm自我刷新:YES
最大待机电流:0.0001 A子类别:DRAMs
最大压摆率:0.055 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

KM44V1004DJ-L7 数据手册

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KM44C1004D, KM44V1004D  
CMOS DRAM  
1M x 4Bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 1,048,576 x 41bit Extended Data Out CMOS DRAMs. Extended Data Out offers high speed random access of memory  
cells within the same row. Power supply voltage (+5V or +3.3V), access time (-5, -6 or -7), power consumption(Normal or Low power),  
and package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh  
and Hidden refresh capabilities.  
This 1Mx4 Extended Data Out DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low  
power consumption and high reliability. It may be used as main memory for main frames and mini computers, personal computer and  
high performance microprocessor systems.  
• Extended Data Out operation  
FEATURES  
CAS-before-RAS refresh capability  
• Part Identification  
RAS-only and Hidden refresh capability  
• Self-refresh capability (3.3V, L-ver only)  
- KM44C1004D/D-L(5V)  
- KM44V1004D/D-L(3.3V)  
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs  
• Early write or output enable controlled write  
JEDEC Standard pinout  
Active Power Dissipation  
Available in 26(20)-pin SOJ 300mil and TSOP(II)  
300mil packages  
Unit : mW  
5V  
Speed  
-5  
3.3V  
-
Single +5V±10% power supply(5V product)  
468  
• Single +3.3V±0.3V power supply(3.3V product)  
-6  
220  
200  
413  
-7  
358  
FUNCTIONAL BLOCK DIAGRAM  
Refresh Cycles  
RAS  
CAS  
W
Vcc  
Vss  
Control  
Clocks  
Part  
NO.  
Refresh  
cycle  
Refresh Period  
VBB Generator  
Normal  
L-ver  
KM44C1004D  
KM44V1004D  
1K  
16ms  
128ms  
Row Decoder  
Refresh Timer  
Refresh Control  
Data in  
Buffer  
Memory Array  
1,048,576 x4  
Cells  
DQ0  
to  
DQ3  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Performance Range  
Spee  
-5  
Remark  
5V only  
tRAC  
50n  
60n  
70n  
tCAC  
tRC  
tHPC  
A0~A9  
Data out  
Buffer  
15ns  
84ns  
20ns  
Column Decoder  
OE  
-6  
15ns 104ns 25ns 5V/3.3V  
20ns 124ns 30ns 5V/3.3V  
-7  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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