Datasheet > KM44V16004BT-45

KM44V16004BT-45

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器光电二极管
页数	文件大小	规格书
21页	420K
描述
EDO DRAM, 16MX4, 45ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32

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KM44V16004BT-45 数据手册

KM44V16004B,KM44V16104B

CMOS DRAM

16M x 4bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random

access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5, or -6), power consumption(Normal

or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh

capabilities. Furthermore, Self-refresh operation is available in L-version. This 16Mx4 EDO Mode DRAM family is fabricated using Sam-

sung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.

• Extended Data Out Mode operation

FEATURES

• CAS-before-RAS refresh capability

• Part Identification

• RAS-only and Hidden refresh capability

• Self-refresh capability (L-ver only)

• Fast parallel test mode capability

• LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

- KM44V16004B/B-L(3.3V, 8K Ref.)

- KM44V16104B/B-L(3.3V, 4K Ref.)

• Active Power Dissipation

Unit : mW

Speed

-45

-5

• Available in Plastic SOJ and TSOP(II) packages

• +3.3V±0.3V power supply

360

324

288

468

432

-6

396

• Refresh Cycles

FUNCTIONAL BLOCK DIAGRAM

Part

NO.

Refresh

cycle

Refresh time

Normal

L-ver

RAS

CAS

Vcc

Vss

Control

Clocks

KM44V16004B*

KM44V16104B

64ms

128ms

VBB Generator

* Access mode & RAS only refresh mode

Row Decoder

Refresh Timer

: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)

CAS-before-RAS & Hidden refresh mode

Data in

Buffer

Refresh Control

Memory Array

: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)

DQ0

DQ3

16,777,216 x 4

Refresh Counter

• Performance Range

Cells

Speed

Data out

Buffer

Row Address Buffer

Col. Address Buffer

tRAC

45ns

50ns

60ns

tCAC

12ns

13ns

15ns

tRC

74ns

84ns

104ns

tHPC

17ns

20ns

25ns

A0~A12

(A0~A11)*1

-45

-5

A0~A10

(A0~A11)*1

Column Decoder

-6

Note) *1 : 4K Refresh

SAMSUNG ELECTRONICS CO., LTD.reserves the right to

change products and specifications without notice.

12 3 4 5 6 7...21

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