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KK74ACT533 PDF预览

KK74ACT533

更新时间: 2024-09-09 05:11:27
品牌 Logo 应用领域
可天士 - KODENSHI 锁存器
页数 文件大小 规格书
6页 376K
描述
Octal 3-State Inverting Transparent Latch High-Speed Silicon-Gate CMOS

KK74ACT533 数据手册

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TECHNICAL DATA  
KK74ACT533  
Octal 3-State Inverting  
Transparent Latch  
High-Speed Silicon-Gate CMOS  
The KK74ACT533 is identical in pinout to the LS/ALS533,  
HC/HCT533. The KK74ACT533 may be used as a level converter for  
interfacing TTL or NMOS outputs to High Speed CMOS inputs.  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. The data appears as the  
outputs in inverted form. When Latch Enable goes low, data meeting the  
setup and hold time becomes latched.  
ORDERING INFORMATION  
KK74ACT533N Plastic  
KK74ACT533DW SOIC  
TA = -40° to 85° C for all packages  
The Output Enable input does not affect the state of the latches, but  
when Output Enable is high, all device outputs are forced to the high-  
impedance state. Thus, data may be latched even when the outputs are not  
enabled.  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA; 0.1 µA @ 25°C  
Outputs Source/Sink 24 mA  
PIN ASSIGNMENT  
3-State Outputs for Bus Interfacing  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
Latch  
Enable Enable  
Output  
Q
Output  
D
L
L
L
H
H
L
H
L
L
H
X
no  
change  
H
X
X
Z
X = don’t care  
Z = high impedance  
P
IN 20=VCC  
PIN 10 = GND  
1

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