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KK74AC373DW PDF预览

KK74AC373DW

更新时间: 2024-11-01 05:11:27
品牌 Logo 应用领域
可天士 - KODENSHI 触发器锁存器
页数 文件大小 规格书
6页 426K
描述
Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

KK74AC373DW 数据手册

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TECHNICAL DATA  
KK74AC373  
Octal 3-State Noninverting  
Transparent Latch  
High-Speed Silicon-Gate CMOS  
The KK74AC373 is identical in pinout to the LS/ALS373,  
HC/HCT373. The device inputs are compatible with standard CMOS  
outputs; with pullup resistors, they are compatible with LS/ALS outputs.  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. When Latch Enable goes  
low, data meeting the setup and hold time becomes latched.  
The Output Enable input does not affect the state of the latches, but  
when Output Enable is high, all device outputs are forced to the high-  
impedance state. Thus, data may be latched even when the outputs are not  
enabled.  
ORDERING INFORMATION  
KK74AC373N Plastic  
KK74AC373DW SOIC  
TA = -40° to 85° C for all packages  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA; 0.1 µA @ 25°C  
High Noise Immunity Characteristic of CMOS Devices  
Outputs Source/Sink 24 mA  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
Latch  
Output  
Q
Output  
D
Enable Enable  
L
L
L
H
H
H
L
H
L
H
L
No Change  
Z
PIN 20=VCC  
PIN 10 = GND  
X
X
X
X = Don’t Care  
Z = High Impedance  
1

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