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KK74AC533DW PDF预览

KK74AC533DW

更新时间: 2024-02-06 04:38:18
品牌 Logo 应用领域
可天士 - KODENSHI 触发器锁存器
页数 文件大小 规格书
6页 412K
描述
Octal 3-State Inverting Transparent Latch High-Speed Silicon-Gate CMOS

KK74AC533DW 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Base Number Matches:1

KK74AC533DW 数据手册

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TECHNICAL DATA  
KK74AC533  
Octal 3-State Inverting  
Transparent Latch  
High-Speed Silicon-Gate CMOS  
The KK74AC533 is identical in pinout to the LS/ALS533,  
HC/HCT533. The device inputs are compatible with standard CMOS  
outputs; with pullup resistors, they are compatible with LS/ALS outputs.  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. The data appears as the  
outputs in inverted form. When Latch Enable goes low, data meeting the  
setup and hold time becomes latched.  
The Output Enable input does not affect the state of the latches, but  
when Output Enable is high, all device outputs are forced to the high-  
impedance state. Thus, data may be latched even when the outputs are not  
enabled.  
ORDERING INFORMATION  
KK74AC533N Plastic  
KK74AC533DW SOIC  
TA = -40° to 85° C for all packages  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA; 0.1 µA @ 25°C  
High Noise Immunity Characteristic of CMOS Devices  
Outputs Source/Sink 24 mA  
PIN ASSIGNMENT  
3-State Outputs for Bus Interfacing  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
Latch  
Enable Enable  
Output  
Q
Output  
D
L
L
L
H
H
L
H
L
L
H
X
no  
change  
H
X
X
Z
X = don’t care  
Z = high impedance  
PIN 20=VCC  
PIN 10 = GND  
1

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