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KK74AC74D PDF预览

KK74AC74D

更新时间: 2024-02-16 00:26:05
品牌 Logo 应用领域
可天士 - KODENSHI 触发器锁存器
页数 文件大小 规格书
6页 396K
描述
Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

KK74AC74D 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:NBase Number Matches:1

KK74AC74D 数据手册

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TECHNICAL DATA  
KK74AC74  
Dual D Flip-Flop with Set and Reset  
High-Speed Silicon-Gate CMOS  
The KK74AC74 is identical in pinout to the LS/ALS74, HC/HCT74.  
The device inputs are compatible with standard CMOS outputs; with  
pullup resistors, they are compatible with LS/ALS outputs.  
This device consists of two D flip-flops with individual Set, Reset,  
and Clock inputs. Information at a D-input is transferred to the  
corresponding Q output on the next positive going edge of the clock input.  
Both Q and Q outputs are available from each flip-flop. The Set and Reset  
inputs are asynchronous.  
ORDERING INFORMATION  
KK74AC74N Plastic  
KK74AC74D SOIC  
TA = -40° to 85° C for all packages  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA; 0.1 µA @ 25°C  
High Noise Immunity Characteristic of CMOS Devices  
Outputs Source/Sink 24 mA  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
Clock  
Outputs  
Set  
L
Reset  
H
Data  
X
Q
Q
X
X
X
H
L
H*  
H
L
L
H
H*  
L
H
L
L
X
L
X
H
H
H
H
H
H
H
H
L
H
H
L
X
No Change  
No Change  
No Change  
H
H
X
PIN 14 =VCC  
PIN 7 = GND  
H
X
*Both outputs will remain high as long as Set  
and Reset are low, but the output states are  
unpredictable if Set and Reset go high  
simultaneously.  
X = don’t care  
1

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