Datasheet > K7M321825M-90

K7M321825M-90

更新时间： 2024-01-09 06:31:36

品牌	Logo	应用领域
三星 - SAMSUNG		静态存储器
页数	文件大小	规格书
5页	34K
描述
SRAM

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技术参数
数据手册

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K7M321825M-90 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

K7M321825M-90 数据手册

K7M323625M

K7M321825M

Preliminary

1Mx36 & 2Mx18 Flow-Through NtRAM^TM

1Mx36 & 2Mx18-Bit Flow Through NtRAM^TM

FEATURES

GENERAL DESCRIPTION

• 3.3V+0.165V/-0.165V Power Supply.

• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O

• Byte Writable Function.

• Enable clock and suspend operation.

• Single READ/WRITE control pin.

• Self-Timed Write Cycle.

• Three Chip Enable for simple depth expansion with no data

contention .

• A interleaved burst or a linear burst mode.

• Asynchronous output enable control.

• Power Down mode.

The K7M323625M and K7M321825M are 37,748,736-bits Syn-

chronous Static SRAMs.

The NtRAM^TM, or No Turnaround Random Access Memory uti-

lizes all bandwidth in any combination of operating cycles.

Address, data inputs, and all control signals except output

enable and linear burst order are synchronized to input clock.

Burst order control must be tied "High or Low".

Asynchronous inputs include the sleep mode enable(ZZ).

Output Enable controls the outputs at any given time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-chip

write pulse generation

• TTL-Level Three-State Outputs.

• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).

and provides increased timing flexibility for incoming signals.

For read cycles, Flow-Through SRAM allows output data to

simply flow freely from the memory array.

FAST ACCESS TIMES

The K7M323625M and K7M321825M are implemented with

SAMSUNG¢s high performance CMOS technology and is avail-

able in 100pin TQFP and 119BGA packages. Multiple power

and ground pins minimize ground bounce.

Parameter

Cycle Time

Symbol -65 -75 -85 -90 Unit

tCYC

tCD

7.5 8.5 10 10 ns

6.5 7.5 8.5 9.0 ns

3.5 3.5 4.0 4.0 ns

Clock Access Time

Output Enable Access Time

tOE

LOGIC BLOCK DIAGRAM

LBO

BURST

ADDRESS

COUNTER

A¢0~A¢1

A [0:19]or

A [0:20]

A0~A1

A2~A19 or A2~A20

1Mx36 , 2Mx18

MEMORY

ARRAY

ADDRESS

WRITE

ADDRESS

CLK

CKE

DATA-IN

CS1

CS2

ADV

CONTROL

LOGIC

BWx

(x=a,b,c,d or a,b)

BUFFER

36 or 18

DQa0 ~ DQd7 orDQa0 ~ DQb8

DQPa ~ DQPd

NtRAM and No Turnaround Random Access Memory are trademarks of Samsung.

- 1 -

May 2001

Rev 0.0

12 3 4 5

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