Datasheet > K7J321882C-FI330

K7J321882C-FI330

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
三星 - SAMSUNG		双倍数据速率静态存储器
页数	文件大小	规格书
18页	409K
描述
DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165

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K7J321882C-FI330 数据手册

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K7J323682C

K7J321882C

1Mx36 & 2Mx18 DDR II SIO b2 SRAM

Single Clock Mode

K7J323682C and K7J321882C can be operated with the single clock pair K and K, instead of C or C for output clocks.

To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high during oper-

ation. After power up, this device can′t change to or from single clock mode. System flight time and clock skew could not be compen-

sated in this mode.

Depth Expansion

Separate input and output ports enables easy depth expansion. Each port can be selected and deselected independently with R/W

be shared among all SRAMs and provide a new LD signal for each bank. Before chip deselected, all read and write pending opera-

tions are completed.

Programmable Impedance Output Buffer Operation

The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor (RQ).

The value of RQ (within 15%) is five times the output impedance desired. For example, 250Ω resistor will give an output impedance

of 50Ω.

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates

are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM.

There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the

SRAM needs 1024 non-read cycles.

Echo clock operation

To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are syn-

chronized with internal data output. Echo clocks run free during normal operation.

The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver.

Clock Consideration

K7J323682C and K7J321882C utilizes internal DLL (Delay-Locked Loops) for maximum output data valid window. It can be placed

into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.

Circuitry automatically resets the DLL when absence of input clock is detected.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied

simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ

does not exceed VDD by more than 0.5V during power-down.

Rev. 1.1 August 2006

- 7 -

1...4 5 678 9 10...18

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与K7J321882C-FI330相关器件

型号	品牌	描述	获取价格	数据表
K7J321882M	SAMSUNG	1Mx36 & 2Mx18 DDR II SIO b2 SRAM	获取价格
K7J321882M-FC13	SAMSUNG	DDR SRAM, 2MX18, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	获取价格
K7J321882M-FC160	SAMSUNG	DDR SRAM, 2MX18, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	获取价格
K7J321882M-FC20	SAMSUNG	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	获取价格
K7J321882M-FC200	SAMSUNG	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	获取价格
K7J321882M-FC20T	SAMSUNG	SRAM	获取价格

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