K7J323682C
K7J321882C
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
GENERAL DESCRIPTION
The K7J323682C and K7J321882C are 37,748,736-bits DDR Separate I/O Synchronous Pipelined Burst SRAMs. They are orga-
nized as 1,048,576 words by 36bits for K7J323682C and 2,097,152 words by 18 bits for K7J321882C.
The DDR SIO operation is possible by supporting DDR read and write operations through separate data output and input ports. Mem-
ory bandwidth is higher than DDR SRAM without separate input output as separate read and write ports eliminate bus turn around
cycle.
Address, data inputs, and all control signals are synchronized to the input clock (K or K). Normally data outputs are synchronized to
output clocks (C and C), but when C and C are tied high, the data outputs are synchronized to the input clocks (K and K). Read data
are referenced to echo clock (CQ or CQ) outputs. Read address and write address are registered on rising edges of the input K
clocks.
Common address bus is used to access address both for read and write operations. The internal burst counter is fixed to 2-bit
sequential for both read and write operations. Synchronous pipeline read and late write enable high speed operations. Simple depth
expansion is accomplished by using LD for port selection. Byte write operation is supported with BW0 and BW1 (BW2 and BW3) pins
for x18 (x36) device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.
The K7J323682C and K7J321882C are implemented with SAMSUNG's high performance 6T CMOS technology and is available in
165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K. Address is presented and stored in
the read address register synchronized with K clock. For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with
each read command.
The first pipelined data is transferred out of the device triggered by C clock following next K clock rising edge. Next burst data is trig-
gered by the rising edge of following C clock rising edge. Continuous read operations are initiated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks. In case C and C tied to high, output data
are triggered by K and K instead of C and C.
When the LD is disabled after a read operation, the K7J323682C and K7J321882C will first complete burst read operation before
entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state.
Write Operations
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K. Address is presented and stored in
the write address register synchronized with next K clock. For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words
with each write command.
The first “late write” data is transferred and registered in to the device synchronous with next K clock rising edge. Next burst data is
transferred and registered synchronous with following K clock rising edge. Continuous write operations are initiated with K rising
edge.
And “late write” data is presented to the device on every rising edge of both K and K clocks.
When the LD is disabled, the K7J323682C and K7J321882C will enter into deselect mode. The device disregards input data pre-
sented on the same cycle W disabled.
The K7J323682C and K7J321882C support byte write operations.
With activating BW0 or BW1 (BW2 or BW3) in write cycle, only one byte of input data is presented. In K7J321882C, BW0 controls write
operation to D0:D8, BW1 controls write operation to D9:D17. And in K7J323682C BW2 controls write operation to D18:D26, BW3 con-
trols write operation to D27:D35.
Rev. 1.1 August 2006
- 6 -
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