K7J323682M
K7J321882M
K7J320882M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDR II SIO b2 SRAM
Document Title
1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDR II SIO b2 SRAM
Revision History
Draft Date
Remark
Rev. No.
History
Advance
Preliminary
July, 15 200 1
Dec, 14 2001
0.0
1. Initial document.
0.1
1. Pin name change from DLL to Doff
2. Update JTAG test conditions.
3. Reserved pin for high density name change from NC to Vss/SA
4. Delete AC test condition about Clock Input timing Reference Level
5. Delete clock description on page 2 and add HSTL I/O comment
6. Deleted R/W control pin description on page 2
Preliminary
Preliminary
Preliminary
July, 29. 2002
Sep. 6. 2002
Oct. 7. 2002
0.2
0.3
0.4
1. Update current characteristics in DC electrical characteristics
2. Change AC timing characteristics
3. Update JTAG instruction coding and diagrams
1. Add AC electrical characteristics.
2. Change AC timing characteristics.
3. Change DC electrical characteristics(ISB1)
1. Change the data Setup/Hold time.
2. Change the Access Time.(tCHQV, tCHQX, etc.)
3. Change the Clock Cycle Time.(MAX value of tKHKH)
4. Change the JTAG instruction coding.
Preliminary
Preliminary
Dec. 16, 2002
Dec. 26, 2002
0.5
0.6
1. Change the Boundary scan exit order.
2. Change the AC timing characteristics(-25, -20)
3. Correct the Overshoot and Undershoot timing diagrams.
1. Change the JTAG Block diagram
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Dec. 2002
Rev 0.6
- 1 -