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K4T1G164QD PDF预览

K4T1G164QD

更新时间: 2024-01-02 12:39:32
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三星 - SAMSUNG 动态存储器双倍数据速率
页数 文件大小 规格书
27页 587K
描述
1Gb D-die DDR2 SDRAM Specification

K4T1G164QD 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:BGA, BGA92,9X21,32
Reach Compliance Code:compliant风险等级:5.84
访问模式:MULTI BANK PAGE BURST最长访问时间:0.6 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMON交错的突发长度:4,8
JESD-30 代码:R-PBGA-B92长度:21.7 mm
内存密度:1073741824 bit内存集成电路类型:DDR DRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:1
端子数量:92字数:67108864 words
字数代码:64000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:64MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA92,9X21,32封装形状:RECTANGULAR
封装形式:GRID ARRAY峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
刷新周期:8192座面最大高度:1.2 mm
自我刷新:YES连续突发长度:4,8
子类别:DRAMs最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11 mm

K4T1G164QD 数据手册

 浏览型号K4T1G164QD的Datasheet PDF文件第19页浏览型号K4T1G164QD的Datasheet PDF文件第20页浏览型号K4T1G164QD的Datasheet PDF文件第21页浏览型号K4T1G164QD的Datasheet PDF文件第23页浏览型号K4T1G164QD的Datasheet PDF文件第24页浏览型号K4T1G164QD的Datasheet PDF文件第25页 
K4T1G084QD  
K4T1G164QD  
DDR2 SDRAM  
4. Differential data strobe  
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode  
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode  
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential  
mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guar-  
anteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be  
tied externally to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.  
t
t
DQSL  
DQSH  
DQS  
DQS  
DQS/  
DQS  
t
t
WPST  
WPRE  
VIH(dc)  
VIL(dc)  
VIH(ac)  
DQ  
DM  
D
D
D
D
t
VIL(ac)  
t
t
DH  
DH  
DS  
t
DS  
VIH(ac)  
VIH(dc)  
DMin  
DMin  
DMin  
DMin  
VIL(ac)  
VIL(dc)  
<Data input (write) timing>  
t
t
CL  
CH  
CK  
CK  
CK/CK  
DQS  
DQS  
DQS/DQS  
DQ  
t
t
RPRE  
RPST  
Q
Q
Q
Q
t
DQSQmax  
t
DQSQmax  
t
t
QH  
QH  
<Data output (read) timing>  
5. AC timings are for linear signal transitions.  
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester  
correlation.  
7. All voltages are referenced to VSS.  
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related  
specifications and device operation are guaranteed for the full voltage range specified.  
20 of 29  
Rev. 1.0 March 2007  

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