Datasheet > K4S640832D-TC/L1H

K4S640832D-TC/L1H

更新时间： 2022-12-12 15:44:23

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器
页数	文件大小	规格书
10页	130K
描述
64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL

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K4S640832D-TC/L1H 数据手册

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K4S640832D

CMOS SDRAM

SIMPLIFIED TRUTH TABLE

11,

CKEn-1 CKEn

RAS

CAS

DQM BA0,1

A10/AP

Note

Command

~ A

Refresh

Mode register set

Auto refresh

OP code

1,2

Entry

Self

refresh

Exit

Bank active & row addr.

Row address

Column

address

(A0 ~ A8)

Read &

column address

Auto precharge disable

Auto precharge enable

Auto precharge disable

Auto precharge enable

4,5

Column

address

(A0 ~ A8)

Write &

Column Address

4,5

Burst stop

Precharge

Bank selection

All banks

Entry

Clock suspend or

active power down

Exit

Entry

Precharge power down mode

Exit

DQM

No operation command

(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)

Notes :

1. OP Code : Operand code

A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev. 0.0 May 1999

1...7 8 910

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