Datasheet > 存储 > DRAM> K4S560832D-TL7A

K4S560832D-TL7A

更新时间： 2024-11-20 23:16:47

品牌	Logo	应用领域
三星 - SAMSUNG		光电二极管动态存储器
页数	文件大小	规格书
11页	153K
描述
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD

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K4S560832D-TL7A 数据手册

M366S3253DTS

PC133/PC100 Unbuffered DIMM

M366S3253DTS SDRAM DIMM

32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD

FEATURE

GENERAL DESCRIPTION

• Performance range

1 The Samsung M366S3253DTS is a 32M bit x 64 Synchronous

Dynamic RAM high density memory module. The Samsung

M366S325DCTS consists of eight CMOS 32M x 8 bit with 4banks

Synchronous DRAMs in TSOP-II 400mil package and a 2K

EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy sub-

strate. Two 0.1uF decoupling capacitors are mounted on the

printed circuit board in parallel for each SDRAM.

Part No.

Max Freq. (Speed)

133MHz (7.5ns@CL=2)

133MHz (7.5ns@CL=3)

100MHz (6.0ns@CL=2)

100MHz (6.0ns@CL=3)

M366S3253DTS-L7C/C7C

M366S3253DTS-L7A/C7A

M366S3253DTS-L1H/C1H

M366S3253DTS-L1L/C1L

• Burst mode operation

The M366S325DCTS is a Dual In-line Memory Module and is

intended for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use of

system clock. I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable latencies allows

the same device to be useful for a variety of high bandwidth, high

performance memory system applications.

• Auto & self refresh capability (8192 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V ± 0.3V power supply

• MRS cycle with address key programs

Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

• Serial presence detect with EEPROM

• PCB : Height (1,375mil), single sided component

PIN CONFIGURATIONS (Front side/back side)

PIN NAMES

Pin Front Pin Front

Front Pin Back Pin Back Pin Back

Pin Name

A0 ~ A12

BA0 ~ BA1

DQ0 ~ DQ63

CLK0, CLK2

CKE0

Function

Address input (Multiplexed)

Select bank

VSS

29 DQM1

DQ18 85

DQ19 86 DQ32 114 *CS1 142 DQ51

87 DQ33 115 RAS 143 VDD

DQ20 88 DQ34 116 VSS 144 DQ52

VSS 113 DQM5 141 DQ50

DQ0 30

DQ1 31

DQ2 32

DQ3 33

CS0

VSS

Data input/output

Clock input

VDD

*VREF 90

*CKE1 91 DQ36 119

92 DQ37 120

DQ21 93 DQ38 121

89 DQ35 117

145 NC

146 *VREF

147 NC

148 VSS

149 DQ53

Clock enable input

Chip select input

Row address strobe

Column address strobe

Write enable

VDD

VDD 118

CS0, CS2

RAS

DQ4 35

DQ5 36

DQ6 37

VSS

CAS

10 DQ7 38 A10/AP

DQ22 94 DQ39 122 BA0 150 DQ54

DQ23 95 DQ40 123 A11 151 DQ55

11 DQ8 39

12 40

13 DQ9 41

BA1

VDD

DQM0 ~ 7

VDD

DQM

VSS

VSS 124 VDD 152 VSS

DQ24 97 DQ41 125 *CLK1 153 DQ56

DQ25 98 DQ42 126 A12 154 DQ57

DQ26 99 DQ43 127 VSS 155 DQ58

DQ27 100 DQ44 128 CKE0 156 DQ59

VDD 101 DQ45 129 *CS3 157 VDD

DQ28 102 VDD 130 DQM6 158 DQ60

DQ29 103 DQ46 131 DQM7 159 DQ61

DQ30 104 DQ47 132 *A13 160 DQ62

DQ31 105 *CB4 133 VDD 161 DQ63

Power supply (3.3V)

Ground

14 DQ10 42 CLK0

VSS

15 DQ11 43

16 DQ12 44

17 DQ13 45

VSS

CS2

*VREF

Power supply for reference

Serial data I/O

SDA

VDD

46 DQM2

SCL

Serial clock

19 DQ14 47 DQM3

SA0 ~ 2

*WP

Address in EEPROM

Write protection

Don¢t use

20 DQ15 48

21 *CB0 49

22 *CB1 50

VDD

VSS 106 *CB5 134

CLK2 107 VSS 135

NC 162 VSS

NC 163 *CLK3

VSS

VDD

No connection

52 *CB2

53 *CB3

NC 108 NC 136 *CB6 164 NC

*WP 109 NC 137 *CB7 165 **SA0

**SDA 110 VDD 138 VSS 166 **SA1

These pins are not used in this module.

** These pins should be NC in the system

VSS

55 DQ16 83 **SCL 111 CAS 139 DQ48 167 **SA2

which does not support SPD.

28 DQM0 56 DQ17

VDD 112 DQM4 140 DQ49 168 VDD

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

REV. 0.0 Jan. 2002

12 3 4 5 6 7...11

中文翻译

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与K4S560832D-TL7A相关器件

型号	品牌	获取价格	描述	数据表
K4S560832D-TL7C	SAMSUNG	获取价格	32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
K4S560832E-NC75	SAMSUNG	获取价格	256Mb E-die SDRAM Specification 54pin sTSOP-II
K4S560832E-NC750	SAMSUNG	获取价格	Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.300 INCH, STSOP2-54
K4S560832E-NL75	SAMSUNG	获取价格	256Mb E-die SDRAM Specification 54pin sTSOP-II
K4S560832E-NL750	SAMSUNG	获取价格	Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.300 INCH, STSOP2-54
K4S560832E-TC75	SAMSUNG	获取价格	256Mb E-die SDRAM Specification
K4S560832E-TC750	SAMSUNG	获取价格	Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
K4S560832E-TC75T	SAMSUNG	获取价格	Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
K4S560832E-TL75	SAMSUNG	获取价格	256Mb E-die SDRAM Specification
K4S560832E-TL750	SAMSUNG	获取价格	Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

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