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K4S51323PF-EF900 PDF预览

K4S51323PF-EF900

更新时间: 2024-11-21 15:36:03
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器内存集成电路
页数 文件大小 规格书
12页 142K
描述
Synchronous DRAM, 16MX32, 7ns, CMOS, PBGA90, LEAD FREE, FBGA-90

K4S51323PF-EF900 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:LFBGA,
针数:90Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.28
风险等级:5.83访问模式:FOUR BANK PAGE BURST
最长访问时间:7 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PBGA-B90JESD-609代码:e1
长度:13 mm内存密度:536870912 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:32
湿度敏感等级:3功能数量:1
端口数量:1端子数量:90
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:-25 °C组织:16MX32
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.4 mm自我刷新:YES
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11 mm
Base Number Matches:1

K4S51323PF-EF900 数据手册

 浏览型号K4S51323PF-EF900的Datasheet PDF文件第2页浏览型号K4S51323PF-EF900的Datasheet PDF文件第3页浏览型号K4S51323PF-EF900的Datasheet PDF文件第4页浏览型号K4S51323PF-EF900的Datasheet PDF文件第5页浏览型号K4S51323PF-EF900的Datasheet PDF文件第6页浏览型号K4S51323PF-EF900的Datasheet PDF文件第7页 
K4S51323PF-M(E)F  
Mobile-SDRAM  
4M x 32Bit x 4 Banks Mobile-SDRAM  
FEATURES  
GENERAL DESCRIPTION  
• 1.8V power supply.  
The K4S51323PF is 536,870,912 bits synchronous high data  
rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits,  
fabricated with SAMSUNG’s high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock and I/O transactions are possible on every  
clock cycle. Range of operating frequencies, programmable  
burst lengths and programmable latencies allow the same  
device to be useful for a variety of high bandwidth and high per-  
• LVCMOS compatible with multiplexed address.  
• Four banks operation.  
• MRS cycle with address key programs.  
-. CAS latency (1, 2 & 3).  
-. Burst length (1, 2, 4, 8 & Full page).  
-. Burst type (Sequential & Interleave).  
• EMRS cycle with address key programs.  
• All inputs are sampled at the positive going edge of the system formance memory system applications.  
clock.  
• Burst read single-bit write operation.  
• Special Function Support.  
-. PASR (Partial Array Self Refresh).  
-. Internal TCSR (Temperature Compensated Self Refresh)  
-. DS (Driver Strength)  
• DQM for masking.  
• Auto refresh.  
• 64ms refresh period (8K cycle).  
• Commercial Temperature Operation (-25°C ~ 70°C).  
• 2Chips DDP 90Balls FBGA( -MXXX -Pb, -EXXX -Pb Free).  
ORDERING INFORMATION  
Part No.  
Max Freq.  
Interface  
Package  
K4S51323PF-M(E)F75  
K4S51323PF-M(E)F90  
K4S51323PF-M(E)F1L  
133MHz(CL=3),83MHz(CL=2)  
111MHz(CL=3),83MHz(CL=2)  
90 FBGA Pb  
(Pb Free)  
LVCMOS  
111MHz(CL=3)*1,66MHz(CL2)  
- M(E)F : Low Power, Commercial Temperature(-25°C ~ 70°C)  
Notes :  
1. In case of 40MHz Frequency, CL1 can be supported.  
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is  
potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product  
contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.  
Address configuration  
Organization  
Bank  
Row  
Column Address  
16Mx32  
BA0,BA1  
A0 - A12  
A0 - A8  
1
September 2004  

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