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K4H560438D-GLA20 PDF预览

K4H560438D-GLA20

更新时间： 2024-01-26 05:44:15
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
26页 291K
描述
DDR DRAM, 64MX4, 0.75ns, CMOS, PBGA60, FBGA-60

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K4H560438D-GLA20 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：TBGA,针数：60
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.24风险等级：5.29
访问模式：FOUR BANK PAGE BURST最长访问时间：0.75 ns
其他特性：AUTO/SELF REFRESHJESD-30 代码：R-PBGA-B60
长度：14 mm内存密度：268435456 bit
内存集成电路类型：DDR DRAM内存宽度：4
功能数量：1端口数量：1
端子数量：60字数：67108864 words
字数代码：64000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64MX4封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE认证状态：Not Qualified
座面最大高度：1.2 mm自我刷新：YES
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM宽度：8 mm
Base Number Matches：1

K4H560438D-GLA20 数据手册

 浏览型号K4H560438D-GLA20的Datasheet PDF文件第7页浏览型号K4H560438D-GLA20的Datasheet PDF文件第8页浏览型号K4H560438D-GLA20的Datasheet PDF文件第9页浏览型号K4H560438D-GLA20的Datasheet PDF文件第11页浏览型号K4H560438D-GLA20的Datasheet PDF文件第12页浏览型号K4H560438D-GLA20的Datasheet PDF文件第13页 
K4H560438D  
DDR SDRAM  
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on  
VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise  
coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.  
2. V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to  
TT  
TT  
VREF, and must track variations in the DC level of VREF  
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.  
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in  
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.  
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.  
DDR SDRAM IDD spec table  
(VDD=2.7V, T = 10°C)  
64Mx4  
Symbol  
Unit  
Notes  
K4H560438D-GC(L)B3  
(DDR333)  
K4H560438D-GC(L)A2,B0  
(DDR266A/B)  
IDD0  
IDD1  
90  
110  
3
80  
100  
3
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2F  
IDD2Q  
IDD3P  
IDD3N  
IDD4R  
IDD4W  
IDD5  
25  
20  
20  
18  
35  
30  
55  
45  
150  
160  
180  
3
120  
135  
165  
3
IDD6  
Normal  
Low power  
1.5  
290  
1.5  
250  
Optional  
IDD7A  
AC Operating Conditions  
Max  
Parameter/Condition  
Symbol  
Min  
Unit  
Note  
Input High (Logic 1) Voltage, DQ, DQS and DM signals  
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.  
Input Differential Voltage, CK and CK inputs  
VIH(AC)  
VIL(AC)  
VID(AC)  
VREF + 0.31  
V
V
V
V
3
3
1
2
VREF - 0.31  
VDDQ+0.6  
0.7  
Input Crossing Point Voltage, CK and CK inputs  
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2  
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.  
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.  
IX  
DDQ  
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu  
lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.  
Overshoot/Undershoot specification  
Specification  
Parameter  
Address &  
Control pins  
Data pins  
Maximum peak amplitude allowed for overshoot  
1.6 V  
1.6 V  
1.2V  
1.2V  
Maximum peak amplitude allowed for undershoot  
The area between the overshoot signal and VDD must be less than or equal to  
The area between the undershoot signal and GND must be less than or equal to  
4.5 V-ns  
4.5 V-ns  
2.5 V-ns  
2.5 V-ns  
Rev. 2.2 Mar. ’03  
- 10 -  
1...78910111213...26

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