Datasheet > K4H560438D-GLA20

K4H560438D-GLA20

更新时间： 2024-01-01 22:01:29

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器双倍数据速率内存集成电路
页数	文件大小	规格书
26页	291K
描述
DDR DRAM, 64MX4, 0.75ns, CMOS, PBGA60, FBGA-60

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K4H560438D-GLA20 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	TBGA,	针数：	60
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.24	风险等级：	5.29
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	0.75 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-PBGA-B60
长度：	14 mm	内存密度：	268435456 bit
内存集成电路类型：	DDR DRAM	内存宽度：	4
功能数量：	1	端口数量：	1
端子数量：	60	字数：	67108864 words
字数代码：	64000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64MX4	封装主体材料：	PLASTIC/EPOXY
封装代码：	TBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	认证状态：	Not Qualified
座面最大高度：	1.2 mm	自我刷新：	YES
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	8 mm
Base Number Matches：	1

K4H560438D-GLA20 数据手册

浏览型号K4H560438D-GLA20的Datasheet PDF文件第10页

256Mb

DDR SDRAM

Input/Output Function Description

SYMBOL

TYPE

DESCRIPTION

CK, CK

Input

Clock : CK and CK are differential clock inputs. All address and control input signals are sam-

pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to

both edges of CK. Internal clock signals are derived from CK/CK.

CKE

Input

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Deactivating the clock provides PRECHARGE

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN

(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,

which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled

during power-down and self refresh modes, providing low standby power. CKE will recognize

an LVCMOS LOW level prior to VREF being stable on power-up.

Input

Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command

decoder. All commands are masked when CS is registered HIGH. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the command code.

RAS, CAS, WE

LDM,(U)DM

Input

Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled on both

edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-

ing. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on

DQ8-DQ15.

BA0, BA1

A [n : 0]

Input

Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-

CHARGE command is being applied.

Address Inputs : Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A10 is sampled during a PRECHARGE command to

determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address

inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1

define which mode register is loaded during the MODE REGISTER SET command (MRS or

EMRS).

I/O

Data Input/Output : Data bus

LDQS,(U)DQS

Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on

DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.

No Connect : No internal electrical connection is present.

DQ Power Supply : +2.5V ± 0.2V.

DQ Ground.

VDDQ

VSSQ

VDD

Supply

Input

Power Supply : +2.5V ± 0.2V (device specific).

Ground.

VSS

VREF

SSTL_2 reference voltage.

Rev. 2.2 Mar. ’03

- 7 -

1...4 5 678 9 10...26

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