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K4E641612C-TL60TN PDF预览

K4E641612C-TL60TN

更新时间: 2024-02-25 21:06:26
品牌 Logo 应用领域
三星 - SAMSUNG 存储内存集成电路光电二极管动态存储器
页数 文件大小 规格书
36页 885K
描述
EDO DRAM, 4MX16, 60ns, CMOS, PDSO50

K4E641612C-TL60TN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSOP, TSOP50,.46,32Reach Compliance Code:unknown
风险等级:5.92最长访问时间:60 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G50
JESD-609代码:e0内存密度:67108864 bit
内存集成电路类型:EDO DRAM内存宽度:16
端子数量:50字数:4194304 words
字数代码:4000000最高工作温度:70 °C
最低工作温度:组织:4MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP封装等效代码:TSOP50,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
电源:3.3 V认证状态:Not Qualified
刷新周期:4096自我刷新:YES
最大待机电流:0.0002 A子类别:DRAMs
最大压摆率:0.11 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUALBase Number Matches:1

K4E641612C-TL60TN 数据手册

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K4E661612C,K4E641612C  
CMOS DRAM  
4M x 16bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random  
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-  
mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden  
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated  
using Samsung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.  
FEATURES  
• Extended Data Out Mode operation  
• 2 CAS Byte/Word Read/Write operation  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Fast parallel test mode capability  
• Self-refresh capability (L-ver only)  
• LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
• Part Identification  
- K4E661612C-TC/L(3.3V, 8K Ref.)  
- K4E641612C-TC/L(3.3V, 4K Ref.)  
ActivePowerDissipation  
Unit : mW  
4K  
Speed  
-45  
8K  
• Available in Plastic TSOP(II) packages  
• +3.3V±0.3V power supply  
324  
288  
252  
468  
-50  
432  
-60  
396  
Refresh Cycles  
FUNCTIONAL BLOCK DIAGRAM  
Part  
NO.  
Refresh  
cycle  
Refresh time  
Normal  
L-ver  
RAS  
UCAS  
LCAS  
W
K4E661612C*  
K4E641612C  
8K  
4K  
Vcc  
Vss  
64ms  
128ms  
Control  
Clocks  
VBB Generator  
* Access mode & RAS only refresh mode  
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)  
CAS-before-RAS & Hidden refresh mode  
Lower  
Data in  
Buffer  
DQ0  
to  
Row Decoder  
Refresh Timer  
DQ7  
Lower  
Data out  
Buffer  
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)  
Refresh Control  
Memory Array  
OE  
4,194,304 x 16  
Cells  
Refresh Counter  
Upper  
Data in  
Buffer  
Performance Range  
DQ8  
to  
DQ15  
Speed  
Row Address Buffer  
Col. Address Buffer  
tRAC  
45ns  
50ns  
60ns  
tCAC  
12ns  
13ns  
15ns  
tRC  
74ns  
84ns  
104ns  
tHPC  
17ns  
20ns  
25ns  
A0~A12  
(A0~A11)*1  
Upper  
Data out  
Buffer  
-45  
-50  
-60  
A0~A8  
(A0~A9)*1  
Column Decoder  
Note) *1 : 4K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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