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K3N7C1000B-YC150 PDF预览

K3N7C1000B-YC150

更新时间: 2024-11-25 14:42:59
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
4页 55K
描述
MASK ROM, 4MX16, 150ns, CMOS, PDSO48, 12 X 18 MM, TSOP1-48

K3N7C1000B-YC150 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSOP1包装说明:TSOP1,
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92Is Samacsys:N
最长访问时间:150 ns备用内存宽度:8
JESD-30 代码:R-PDSO-G48长度:16.4 mm
内存密度:67108864 bit内存集成电路类型:MASK ROM
内存宽度:16功能数量:1
端子数量:48字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX16封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:12 mm
Base Number Matches:1

K3N7C1000B-YC150 数据手册

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K3N7C1000B-YC  
CMOS MASK ROM  
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
8,388,608 x 8(byte mode)  
4,194,304 x 16(word mode)  
· Fast access time :  
100ns(Max.) : CL=50pF  
120ns(Max.) : CL=100pF  
· Supply voltage : single +5.0V  
· Current consumption  
Operating : 70mA(Max.)  
Standby : 100mA(Max.)  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
The K3N7C1000B-YC is a fully static mask programmable  
ROM fabricated using silicon gate CMOS process technology,  
and is organized either as 8,388,608 x 8 bit(byte mode) or as  
4,194,304 x 16 bit(word mode) depending on BHE voltage  
level.(See mode selection table)  
This device operates with 5.0V power supply, and all inputs and  
outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
The K3N7C1000B-YC is packaged in a 48-TSOP1.  
· Package  
K3N7C1000B-YC : 48-TSOP1-1218  
FUNCTIONAL BLOCK DIAGRAM  
Pin Name  
A0 - A21  
Pin Function  
Address Inputs  
A21  
X
MEMORY CELL  
MATRIX  
BUFFERS  
AND  
Q0 - Q14  
Data Outputs  
.
.
.
.
.
.
.
.
(4,194,304x16/  
8,388,608x8)  
Output 15(Word mode)/  
LSB Address(Byte mode)  
Q15 /A-1  
DECODER  
BHE  
CE  
Word/Byte selection  
Chip Enable  
Y
SENSE AMP.  
OE  
Output Enable  
Power (+5V)  
Ground  
BUFFERS  
AND  
VCC  
Vss  
N.C  
DATA OUT  
BUFFERS  
DECODER  
A0  
No Connection  
A-1  
.
.
.
CE  
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
OE  
BHE  

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