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K3N7C1000B-GC120 PDF预览

K3N7C1000B-GC120

更新时间: 2024-11-25 20:04:19
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
3页 48K
描述
MASK ROM, 4MX16, 120ns, CMOS, PDSO44, 0.600 INCH, SOP-44

K3N7C1000B-GC120 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:44Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:120 ns
备用内存宽度:8JESD-30 代码:R-PDSO-G44
长度:28.5 mm内存密度:67108864 bit
内存集成电路类型:MASK ROM内存宽度:16
功能数量:1端子数量:44
字数:4194304 words字数代码:4000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX16
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
认证状态:Not Qualified座面最大高度:3.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:12.6 mmBase Number Matches:1

K3N7C1000B-GC120 数据手册

 浏览型号K3N7C1000B-GC120的Datasheet PDF文件第2页浏览型号K3N7C1000B-GC120的Datasheet PDF文件第3页 
K3N7C1000B-GC  
CMOS MASK ROM  
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
8,388,608 x 8(byte mode)  
4,194,304 x 16(word mode)  
· Fast access time :  
100ns(Max.) : CL=50pF  
120ns(Max.) : CL=100pF  
· Supply voltage : single +5V  
· Current consumption  
Operating : 70mA(Max.)  
Standby : 50mA(Max.)  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
The K3N7C1000B-GC is a fully static mask programmable  
ROM fabricated using silicon gate CMOS process technology,  
and is organized either as 8,388,608 x 8 bit(byte mode) or as  
4,194,304 x 16 bit(word mode) depending on BHE voltage  
level.(See mode selection table)  
This device operates with a 5V single power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
The K3N7C1000B-GC is packaged in a 44-SOP.  
· Package  
-. K3N7C1000B-GC : 44-SOP-600  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A21  
X
MEMORY CELL  
MATRIX  
(4,194,304x16/  
8,388,608x8)  
A20  
A19  
A8  
1
2
44  
43  
42  
41  
40  
39  
A21  
A18  
BUFFERS  
AND  
DECODER  
.
.
.
.
.
.
.
.
A17  
A7  
3
4
A9  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
A10  
A11  
5
6
Y
38 A12  
37 A13  
7
SENSE AMP.  
BUFFERS  
AND  
DECODER  
8
DATA OUT  
BUFFERS  
A14  
36  
9
A0  
A15  
35  
10  
11  
A16  
34  
33  
SOP  
A-1  
CE 12  
BHE  
.
.
.
VSS  
13  
32 VSS  
OE 14  
Q15/A-1  
31  
30  
29  
28  
27  
26  
25  
24  
23  
CE  
Q7  
Q0  
Q8  
15  
16  
17  
18  
19  
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
Q14  
Q6  
OE  
Q1  
Q9  
BHE  
Q13  
Q5  
Q2  
Q10 20  
Q12  
Q4  
Pin Name  
A0 - A21  
Pin Function  
Q3  
21  
22  
Address Inputs  
Data Outputs  
Q11  
VCC  
Q0 - Q14  
Q15 /A-1  
Output 15(Word mode)/  
LSB Address(Byte mode)  
K3N7C1000B-GC  
BHE  
CE  
Word/Byte selection  
Chip Enable  
Output Enable  
Power ( +5V)  
Ground  
OE  
VCC  
VSS  

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