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K3N3V3000D-GC PDF预览

K3N3V3000D-GC

更新时间: 2024-11-30 19:29:55
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
3页 45K
描述
MASK ROM, 512KX8, 100ns, CMOS, PDSO32

K3N3V3000D-GC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP32,.56Reach Compliance Code:unknown
风险等级:5.92最长访问时间:100 ns
JESD-30 代码:R-PDSO-G32JESD-609代码:e0
内存密度:4194304 bit内存集成电路类型:MASK ROM
内存宽度:8端子数量:32
字数:524288 words字数代码:512000
最高工作温度:70 °C最低工作温度:
组织:512KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP32,.56
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.00003 A子类别:MASK ROMs
最大压摆率:0.025 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

K3N3V3000D-GC 数据手册

 浏览型号K3N3V3000D-GC的Datasheet PDF文件第2页浏览型号K3N3V3000D-GC的Datasheet PDF文件第3页 
K3N3V(U)3000D-D(G)C  
CMOS MASK ROM  
4M-Bit (512Kx8) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
The K3N3V(U)3000D-D(G)C is a fully static mask programma-  
ble ROM organized 524,288 x 8 bit. It is fabricated using silicon  
gate CMOS process technology.  
· 524,288 x 8 bit organization  
· Fast access time  
3.3V Operation : 100ns(Max.)  
3.0V Operation : 120ns(Max.)  
· Supply voltage : single +3.0V/ single +3.3V  
· Current consumption  
Operating : 25mA(Max.)  
Standby : 30mA(Max.)  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
This device operates with 3.0V or 3.3V power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
The K3N3V(U)3000D-DC is packaged in a 32-DIP and the  
K3N3V(U)3000D-GC in a 32-SOP.  
· Package  
-. K3N3V(U)3000D-DC : 32-DIP-600  
-. K3N3V(U)3000D-GC : 32-SOP-525  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A18  
X
MEMORY CELL  
MATRIX  
BUFFERS  
AND  
.
.
.
.
.
.
.
.
(524,288x8)  
N.C  
A16  
A15  
A12  
A7  
1
2
32 VCC  
31 A18  
DECODER  
A17  
A14  
A13  
A8  
3
30  
29  
28  
27  
26  
25  
24  
23  
4
Y
SENSE AMP.  
BUFFERS  
BUFFERS  
AND  
5
A6  
6
DECODER  
A0  
A5  
A9  
7
DIP  
&
SOP  
A4  
8
A11  
. . .  
A3  
9
OE  
A10  
A2  
10  
CE  
OE  
Q0  
Q7  
A1  
21 CE  
11  
12  
13  
14  
CONTROL  
LOGIC  
A0  
Q7  
21  
Q0  
Q1  
Q2  
VSS  
Q6  
20  
19 Q5  
Q4  
Q3  
15  
16  
18  
17  
Pin Name  
A0 - A18  
Q0 - Q7  
CE  
Pin Function  
Address Inputs  
Data Outputs  
Chip Enable  
Output Enable  
Power  
K3N3V(U)3000D-D(G)C  
OE  
VCC  
VSS  
Ground  
N.C  
No Connection  

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