Datasheet > JS28F512P30BFA

JS28F512P30BFA

更新时间： 2024-01-27 13:33:48

品牌	Logo	应用领域
恒忆 - NUMONYX		光电二极管内存集成电路闪存
页数	文件大小	规格书
82页	979K
描述
Flash, 32MX16, 110ns, PDSO56, LEAD FREE, TSOP-56

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

JS28F512P30BFA 技术参数

生命周期：	Transferred	零件包装代码：	TSOP
包装说明：	LEAD FREE, TSOP-56	针数：	56
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.1.A
HTS代码：	8542.32.00.51	风险等级：	5.46
最长访问时间：	110 ns	启动块：	BOTTOM
JESD-30 代码：	R-PDSO-G56	长度：	18.4 mm
内存密度：	536870912 bit	内存集成电路类型：	FLASH
内存宽度：	16	功能数量：	1
端子数量：	56	字数：	33554432 words
字数代码：	32000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	32MX16	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	并行/串行：	PARALLEL
编程电压：	3 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压 (Vsup)：	2 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
类型：	NOR TYPE	宽度：	14 mm
Base Number Matches：	1

JS28F512P30BFA 数据手册

P30-65nm

1.0

Functional Description

1.1

Introduction

This document provides information about the Numonyx^TMAxcell^TMP30-65nm Flash

memory and describes its features, operations, and specifications.

P30-65nm is the latest generation of Numonyx^TMAxcell^TMP30 Flash memory to the

embedded flash market segment, offered in 64-Mbit up through 2-Gbit. This document

covers specifically 512-Mbit and 1-Gbit product information. Benefits include more

density in less space, high-speed interface NOR device, and support for code and data

storage. Features include high-performance synchronous-burst read mode, a

dramatical improvement in buffer program time through larger buffer size, fast

asynchronous access times, low power, flexible security options, and two industry-

standard package choices.

P30-65nm is manufactured using Numonyx™ 65nm ETOX™ X process technology.

1.2

Overview

P30-65nm device provides high performance on a 16-bit data bus. Individually erasable

memory blocks are sized for optimum code and data storage. Upon initial power-up or

return from reset, the device defaults to asynchronous page-mode read. Configuring

the Read Configuration Register (RCR) enables synchronous burst-mode reads. In

synchronous burst mode, output data is synchronized with a user-supplied clock signal.

A WAIT signal provides easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates

technology that enables fast buffer program and erase operations. The device features

a 512-word buffer to enable optimum programming performance, which can improve

system programming throughput time significantly to 1.46MByte/s.

Designed for low-voltage systems, the P30-65nm device supports read operations with

VCC at 1.8V, and erase and program operations with VPP at 1.8V or 9.0V. Buffered

Enhanced Factory Programming provides the fastest flash array programming

performance with VPP at 9.0V, which increases factory throughput. With VPP at 1.8V,

VCC and VPP can be tied together for a simple, ultra low power design. In addition to

voltage flexibility, a dedicated VPP connection provides complete data protection when

VPP ≤ V_PPLK

The Command User Interface is the interface between the system processor and all

internal operations of the device. An internal Write State Machine automatically

executes the algorithms and timings necessary for block erase and program. A Status

A device command sequence invokes program and erase automation. Each erase

operation erases one block. The Erase Suspend feature allows system software to

pause an erase cycle to read or program data in another block. Program Suspend

allows system software to pause programming to read other locations.

P30-65nm OTP register allows unique flash device identification that can be used to

increase system security. The individual Block Lock feature provides zero-latency block

locking and unlocking. The P30-65nm device adds enhanced protection via Password

Access; this new feature allows write and/or read access protection of user-defined

blocks. In addition, the P30-65nm device also has backward compatible One-Time

Programmable (OTP) permanent block locking security feature.

Datasheet

Aug 2009

OrderNumber:208042-02

1 2 3 456 7 8...82

下载PDF

与JS28F512P30BFA相关器件

型号	品牌	描述	获取价格	数据表
JS28F512P30EF	MICRON	Micron Parallel NOR Flash Embedded Memory (P30-65nm)	获取价格
JS28F512P30EF	NUMONYX	Flash, 32MX16, 110ns, PDSO56, LEAD FREE, TSOP-56	获取价格
JS28F512P30EFA	MICRON	Anticipating electrostatic discharge (ESD) technology roadmap trends with ESD control hard	获取价格
JS28F512P30TF	MICRON	Micron Parallel NOR Flash Embedded Memory (P30-65nm)	获取价格
JS28F512P30TF	NUMONYX	Flash, 32MX16, 110ns, PDSO56, LEAD FREE, TSOP-56	获取价格
JS28F512P30TFA	MICRON	Numonyx Axcell P30-65nm Flash Memory	获取价格

与JS28F512P30BFA相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

15
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

15
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

13
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

10

产品中心

服务支持

精选活动

关于我们

帮助中心

JS28F512P30BFA

JS28F512P30BFA 技术参数

JS28F512P30BFA 数据手册

与JS28F512P30BFA相关器件

与JS28F512P30BFA相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

JS28F512P30BFA

JS28F512P30BFA 技术参数

JS28F512P30BFA 数据手册

与JS28F512P30BFA相关器件

与JS28F512P30BFA相关文章

您还可以找

您在本页遇到什么问题？