Datasheet > JS28F256P33BFA

JS28F256P33BFA

更新时间： 2024-01-18 18:35:33

品牌	Logo	应用领域
镁光 - MICRON		PC
页数	文件大小	规格书
132页	1301K
描述
Anticipating electrostatic discharge (ESD) technology roadmap trends with ESD control hardening precautions for the handling and assembly of semiconductor die, wafers, packages, and PCBs.

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JS28F256P33BFA 数据手册

Micron Confidential and Proprietary

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

General Description

Micron NAND Flash devices include an asynchronous data interface for high-perform-

ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer

commands, address, and data. There are five control signals used to implement the

asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control

hardware write protection and monitor device status (R/B#).

This hardware interface creates a low pin-count device with a standard pinout that re-

mains the same from one density to another, enabling future upgrades to higher densi-

ties with no board redesign.

A target is the unit of memory accessed by a chip enable signal. A target contains one or

more NAND Flash die. A NAND Flash die is the minimum unit that can independently

execute commands and report status. A NAND Flash die, in the ONFI specification, is

referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable

signal. For further details, see Device and Array Organization.

This device has an internal 4-bit ECC that can be enabled using the GET/SET features.

See Internal ECC and Spare Area Mapping for ECC for more information.

Signal Descriptions

Table 1: Signal Definitions

Signal¹

Type

Input

Description²

ALE

Address latch enable: Loads an address from I/O[7:0] into the address register.

CE#

CE#2

Chip enable: Enables or disables one or more die (LUNs) in a target.

For the 16Gb device, CE# controls the first 8Gb of memory; CE2# controls the second 8Gb

of memory.

CLE

Input

Command latch enable: Loads a command from I/O[7:0] into the command register.

LOCK

When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable the

BLOCK LOCK, connect LOCK to V_SSduring power-up, or leave it disconnected (internal

pull-down).

RE#

Input

Read enable: Transfers serial data from the NAND Flash to the host system.

WE#

Write enable: Transfers commands, addresses, and serial data from the host system to the

NAND Flash.

WP#

Input

I/O

Write protect: Enables or disables array PROGRAM and ERASE operations.

I/O[7:0] (x8)

Data inputs/outputs: The bidirectional I/Os transfer address, data, and command infor-

I/O[15:0] (x16)

mation.

R/B#

R/B#2

Output

Ready/busy: An open-drain, active-low output that requires an external pull-up resistor.

This signal indicates target array activity.

For the 16Gb device, R/B# indicates the status of the first 8Gb of memory; R/B# indicates

the status of the second 8Gb of memory.

V_CC

V_SS

Supply

V_CC: Core power supply

Supply

V_SS: Core ground connection

–

No connect: NCs are not internally connected. They can be driven or left unconnected.

Do not use: DNUs must be left unconnected.

DNU

1. See Device and Array Organization for detailed signal connections.

Notes:

PDF: 09005aef83b25735

m60a_4gb_8gb_16gb_ecc_nand.pdf - Rev. N 10/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1...5 6 789 10 11...132

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JS28F256P33BFA 替代型号

型号	品牌	替代类型	描述	数据表
JS28F256P33BFE	MICRON	完全替代	NumonyxTM StrataFlash Embedded Memory

与JS28F256P33BFA相关器件

型号	品牌	获取价格	描述	数据表
JS28F256P33BFE	MICRON	获取价格	NumonyxTM StrataFlash Embedded Memory
JS28F256P33T95	INTEL	获取价格	Flash, 16MX16, 95ns, PDSO56, 14 X 20 MM, LEAD FREE, TSOP-56
JS28F256P33T95A	MICRON	获取价格	64Mb, 128Mb, 256Mb, 512Mb, Multilevel Cell, Parallel NOR Flash Memory
JS28F256P33T95B	NUMONYX	获取价格	Flash, 16MX16, 95ns, PDSO56, 14 X 20 MM, LEAD FREE, TSOP-56
JS28F256P33T95B	MICRON	获取价格	64Mb, 128Mb, 256Mb, 512Mb, Multilevel Cell, Parallel NOR Flash Memory
JS28F256P33TFA	MICRON	获取价格	Anticipating electrostatic discharge (ESD) technology roadmap trends with ESD control hard
JS28F256P33TFE	MICRON	获取价格	Anticipating electrostatic discharge (ESD) technology roadmap trends with ESD control hard
JS28F320B3BD70	INTEL	获取价格	Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, LEAD FREE, TSOP-48
JS28F320B3TD70	INTEL	获取价格	Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, LEAD FREE, TSOP-48
JS28F320C3BD90	NUMONYX	获取价格	Flash, 2MX16, 90ns, PDSO48, 12 X 20 MM, LEAD FREE, TSOP-48

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