Datasheet > JS28F128J3A-110

JS28F128J3A-110

更新时间： 2022-11-25 16:13:17

品牌	Logo	应用领域
英特尔 - INTEL		闪存
页数	文件大小	规格书
72页	909K
描述
Intel StrataFlash Memory (J3)

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JS28F128J3A-110 数据手册

256-Mbit J3 (x8/x16)

1.0

Introduction

This document describes the Intel StrataFlash^®Memory (J3) device. It includes a description of

device features, operations, and specifications.

1.1

Nomenclature

AMIN:

AMIN = A0 for x8

AMIN = A1 for x16

AMAX:

32 Mbit

64 Mbit

128 Mbit

256 Mbit

AMAX = A21

AMAX = A22

AMAX = A23

AMAX = A24

Block:

Clear:

CUI:

MLC:

OTP:

PLR:

PR:

A group of flash cells that share common erase circuitry and erase simultaneously

Indicates a logic zero (0)

Command User Interface

Multi-Level Cell

One Time Programmable

Protection Lock Register

Protection Register

PRD

Protection Register Data

Program: To write data to the flash array

RFU:

Set:

Reserved for Future Use

Indicates a logic one (1)

SR:

Status Register

SRD:

VPEN:

Status Register Data

Refers to a signal or package connection name

Refers to timing or voltage levels

Write State Machine

Extended Configuration Register

eXtended Status Register

V_PEN

WSM:

ECR:

XSR:

1.2

Conventions

0x:

Hexadecimal prefix

0b:

Binary prefix

k (noun):

M (noun):

Nibble

Byte:

Word:

Kword:

Kb:

1,000

1,000,000

4 bits

8 bits

16 bits

1,024 words

1,024 bits

KB:

1,024 bytes

Mb:

1,048,576 bits

MB:

1,048,576 bytes

Brackets:

Square brackets ([]) will be used to designate group membership or to define a

group of signals with similar function (i.e., A[21:1], SR[4,1] and D[15:0]).

Datasheet

1...4 5 678 9 10...72

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