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JANTXVH2N7269U

更新时间： 2023-02-26 15:00:40
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
27页 1035K
描述
Power Field-Effect Transistor, 26A I(D), 200V, 0.1ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET,

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JANTXVH2N7269U 技术参数

是否Rohs认证： 不符合生命周期：Active
Reach Compliance Code：compliantECCN代码：EAR99
风险等级：5.19其他特性：RADIATION HARDENED
雪崩能效等级（Eas）：500 mJ外壳连接：DRAIN
配置：SINGLE最小漏源击穿电压：200 V
最大漏极电流 (Abs) (ID)：26 A最大漏极电流 (ID)：26 A
最大漏源导通电阻：0.1 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：R-XBCC-N3JESD-609代码：e0
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
封装主体材料：UNSPECIFIED封装形状：RECTANGULAR
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：N-CHANNEL最大功率耗散 (Abs)：150 W
最大脉冲漏极电流 (IDM)：104 A认证状态：Qualified
参考标准：MIL-19500/603E子类别：FET General Purpose Power
表面贴装：YES端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管元件材料：SILICON
Base Number Matches：1

JANTXVH2N7269U 数据手册

 浏览型号JANTXVH2N7269U的Datasheet PDF文件第3页浏览型号JANTXVH2N7269U的Datasheet PDF文件第4页浏览型号JANTXVH2N7269U的Datasheet PDF文件第5页浏览型号JANTXVH2N7269U的Datasheet PDF文件第7页浏览型号JANTXVH2N7269U的Datasheet PDF文件第8页浏览型号JANTXVH2N7269U的Datasheet PDF文件第9页 
MIL-PRF-19500/603J  
3. REQUIREMENTS  
3.1 General. The individual item requirements shall be as specified in MIL-PRF-19500 and as modified herein.  
3.2 Qualification. Devices furnished under this specification shall be products that are manufactured by a  
manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturer's list (QML)  
before contract award (see 4.2 and 6.3).  
3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as  
specified in MIL-PRF-19500 and as follows.  
IAS ........ Rated avalanche current, nonrepetitive  
nC ........ nano Coulomb.  
3.4 Interface and physical dimensions. The interface and physical dimensions shall be as specified in  
MIL-PRF-19500 and on figure 1 and 2 herein. Methods used for electrical isolation of the terminal feedthroughs shall  
employ materials that contain a minimum of 90 percent AL2O3 (ceramic). Examples of such construction techniques  
are metallized ceramic eyelets or ceramic walled packages.  
3.4.1 Lead finish. Lead finish shall be solderable in accordance with MIL-PRF-19500, MIL-STD-750, and herein.  
Where a choice of lead finish is desired, it shall be specified in the acquisition document (see 6.2).  
3.4.2 Internal construction. Multiple chip construction is not permitted.  
3.5 Marking. Marking shall be in accordance with MIL-PRF-19500.  
3.6 Electrostatic discharge protection. The devices covered by this specification require electrostatic discharge  
protection.  
3.6.1 Handling. MOS devices must be handled with certain precautions to avoid damage due to the accumulation  
of static charge. However, the following handling practices are recommended (see 3.6).  
a. Devices should be handled on benches with conductive handling devices.  
b. Ground test equipment, tools, and personnel handling devices.  
c. Do not handle devices by the leads.  
d. Store devices in conductive foam or carriers.  
e. Avoid use of plastic, rubber, or silk in MOS areas.  
f. Maintain relative humidity above 50 percent if practical.  
g. Care should be exercised during test and troubleshooting to apply not more than maximum rated voltage to  
any lead.  
h. Gate must be terminated to source, R ≤ 100 kΩ, whenever bias voltage is to be applied drain to source.  
3.7 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance  
characteristics are as specified in 1.3, 1.4, and table I herein.  
3.8 Electrical test requirements. The electrical test requirements shall be as specified in table I.  
3.9 Workmanship. Semiconductor devices shall be processed in such a manner as to be uniform in quality and  
shall be free from other defects that will affect life, serviceability, or appearance.  
6
 
 
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JANTXVIN6626US MICROSEMI

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JANTXVIN6627US MICROSEMI

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