Datasheet > ISPLSI5512VA-110LB388

ISPLSI5512VA-110LB388

更新时间： 2024-10-29 23:59:51

品牌	Logo	应用领域
其他 - ETC		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
26页	331K
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Electrically-Erasable Complex PLD

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ispLSI 5512VA

In-System Programmable

3.3V SuperWIDE™ High Density PLD

— Superior Quality of Results

Features

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

• SuperWIDE HIGH-DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 3.3V Power Supply

— User Selectable 3.3V/2.5V I/O

— 24000 PLD Gates / 512 Macrocells

— Up to 288 I/O Pins

Functional Block Diagram

— 512 Registers

Input Bus

— High-Speed Global Interconnect

— SuperWIDE 32 Generic Logic Block (GLB) Size for

Optimum Performance

Boundary

Scan

Interface

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

— SuperWIDE Input Gating (68 Inputs) for Fast

Counters, State Machines, Address Decoders, etc.

— PCB Efficient Ball Grid Array (BGA) Package

Options

— Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 110 MHz Maximum Operating Frequency

— tpd = 8.5 ns Propagation Delay

— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,

tsu3 (CLK2/3) = 3.5ns

Global Routing Pool

(GRP)

— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path

Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Input Bus

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

3.3V IN-SYSTEM PROGRAMMABLE

ispLSI 5000V Description

The ispLSI 5000V Family of In-System Programmable

High Density Logic Devices is based on Generic Logic

Blocks (GLBs) of 32 registered macrocells and a single

Global Routing Pool (GRP) structure interconnecting the

GLBs.

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture with Single-

Level Global Routing Pool and SuperWIDE GLBs

— Wrap Around Product Term Sharing Array Supports

up to 35 Product Terms Per Macrocell

— Macrocells Support Concurrent Combinatorial and

Registered Functions

— Macrocell Registers Feature Multiple Control

Options Including Set, Reset and Clock Enable

— Four Dedicated Clock Input Pins Plus Macrocell

Product Term Clocks

— Slew and Skew Programmable I/O (SASPI/O™)

Supports Programmable Bus Hold, Pull-up, Open

Drain and Slew and Skew Rate Options

Outputs from the GLBs drive the Global Routing Pool

(GRP) between the GLBs. Switching resources are pro-

vided to allow signals in the Global Routing Pool to drive

any or all the GLBs in the device. This mechanism allows

fast, efficient connections across the entire device.

Each GLB contains 32 macrocells and a fully populated,

programmable AND-array with 160 logic product terms

and five extra control product terms. The GLB has 68

inputs from the Global Routing Pool which are available

in both true and complement form for every product term.

— Six Global Output Enable Terms, Two Global OE

Pins and One Product Term OE per Macrocell

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

5512va_04

12 3 4 5 6 7...26

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与ISPLSI5512VA-110LB388相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI5512VA-110LQ208	ETC	获取价格
ISPLSI5512VA-125LB272	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE⑩ High D
ISPLSI5512VA-125LB388	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE⑩ High D
ISPLSI5512VA-125LQ208	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE⑩ High D
ISPLSI5512VA-70LB272	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE⑩ High D
ISPLSI5512VA-70LB388	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE⑩ High D
ISPLSI5512VA-70LB388I	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI5512VA-70LQ208	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE⑩ High D
ISPLSI5512VE-100LB272	ETC	获取价格
ISPLSI5512VE-100LB272I	ETC	获取价格	Electrically-Erasable Complex PLD

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