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ISPLSI5384VA-100LB208 PDF预览

ISPLSI5384VA-100LB208

更新时间： 2024-10-28 22:16:27
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
28页 350K
描述
In-System Programmable 3.3V SuperWIDE⑩ High Density PLD

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ISPLSI5384VA-100LB208 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：THERMALLY ENHANCED, FBGA-208针数：208
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.85
其他特性：384 MACROCELLS最大时钟频率：69 MHz
系统内可编程：YESJESD-30 代码：S-PBGA-B208
JESD-609代码：e0JTAG BST：YES
长度：17 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：144
宏单元数：384端子数量：208
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 144 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA208,16X16,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：225
电源：2.5/3.3,3.3 V可编程逻辑类型：EE PLD
传播延迟：13 ns认证状态：Not Qualified
座面最大高度：2.1 mm子类别：Programmable Logic Devices
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：17 mm
Base Number Matches：1

ISPLSI5384VA-100LB208 数据手册

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®
ispLSI 5384VA  
In-System Programmable  
3.3V SuperWIDE™ High Density PLD  
— Superior Quality of Results  
Features  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
• SuperWIDE HIGH-DENSITY IN-SYSTEM  
PROGRAMMABLE LOGIC  
— 3.3V Power Supply  
— User Selectable 3.3V/2.5V I/O  
— 18,000 PLD Gates / 384 Macrocells  
— Up to 288 I/O Pins  
Functional Block Diagram  
— 384 Registers  
— High-Speed Global Interconnect  
— SuperWIDE 32 Generic Logic Block (GLB) Size for  
Optimum Performance  
Input Bus  
Input Bus  
Input Bus  
Boundary  
Scan  
Interface  
Generic  
Logic Block  
Generic  
Logic Block  
Generic  
Logic Block  
— SuperWIDE Input Gating (68 Inputs) for Fast  
Counters, State Machines, Address Decoders, etc.  
— PCB Efficient Ball Grid Array (BGA) Package  
Options  
— Interfaces with Standard 5V TTL Devices  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 125 MHz Maximum Operating Frequency  
— tpd = 7.5 ns Propagation Delay  
— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,  
tsu3 (CLK2/3) = 3.5ns  
Global Routing Pool  
(GRP)  
— TTL/3.3V/2.5V Compatible Input Thresholds and  
Output Levels  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
— Programmable Speed/Power Logic Path  
Optimization  
Generic  
Logic Block  
Generic  
Logic Block  
Generic  
Logic Block  
• IN-SYSTEM PROGRAMMABLE  
— Increased Manufacturing Yields, Reduced Time-to-  
Market, and Improved Product Quality  
Input Bus  
Input Bus  
Input Bus  
— Reprogram Soldered Devices for Faster Debugging  
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND  
3.3V IN-SYSTEM PROGRAMMABLE  
ispLSI 5000V Description  
The ispLSI 5000V Family of In-System Programmable  
High Density Logic Devices is based on Generic Logic  
Blocks (GLBs) of 32 registered macrocells and a single  
Global Routing Pool (GRP) structure interconnecting the  
GLBs.  
• ARCHITECTURE FEATURES  
— Enhanced Pin-Locking Architecture with Single-  
Level Global Routing Pool and SuperWIDE GLBs  
— Wrap Around Product Term Sharing Array Supports  
up to 35 Product Terms Per Macrocell  
— Macrocells Support Concurrent Combinatorial and  
Registered Functions  
— Macrocell Registers Feature Multiple Control  
Options Including Set, Reset and Clock Enable  
— Four Dedicated Clock Input Pins Plus Macrocell  
Product Term Clocks  
— Slew and Skew Programmable I/O (SASPI/O™)  
Supports Programmable Bus Hold, Pull-up, Open  
Drain and Slew and Skew Rate Options  
Outputs from the GLBs drive the Global Routing Pool  
(GRP) between the GLBs. Switching resources are pro-  
vided to allow signals in the Global Routing Pool to drive  
any or all the GLBs in the device. This mechanism allows  
fast, efficient connections across the entire device.  
Each GLB contains 32 macrocells and a fully populated,  
programmable AND-array with 160 logic product terms  
and five extra control product terms. The GLB has 68  
inputs from the Global Routing Pool which are available  
in both true and complement form for every product term.  
— Six Global Output Enable Terms, Two Global OE  
Pins and One Product Term OE per Macrocell  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
September 2000  
5384va_04  
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