Datasheet > ISPLSI5384VA-70LB388I

ISPLSI5384VA-70LB388I

更新时间： 2024-10-29 19:37:11

品牌	Logo	应用领域
莱迪思 - LATTICE		时钟输入元件可编程逻辑
页数	文件大小	规格书
31页	305K
描述
EE PLD, 19ns, CMOS, PBGA388, THERMALLY ENHANCED, BGA-388

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ISPLSI5384VA-70LB388I 技术参数

生命周期：	Obsolete	包装说明：	BGA,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.82
其他特性：	384 MACROCELLS	最大时钟频率：	45 MHz
JESD-30 代码：	S-PBGA-B388	长度：	35 mm
专用输入次数：		I/O 线路数量：	288
端子数量：	388	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	0 DEDICATED INPUTS, 288 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	可编程逻辑类型：	EE PLD
传播延迟：	19 ns	座面最大高度：	3.25 mm
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	宽度：	35 mm
Base Number Matches：	1

ISPLSI5384VA-70LB388I 数据手册

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ispLSI 5384VA

In-System Programmable

3.3V SuperWIDE™ High Density PLD

Features

Functional Block Diagram

• SuperWIDE HIGH-DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 3.3V Power Supply

Input Bus

Boundary

Scan

Interface

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

— User Selectable 3.3V/2.5V I/O

— 18,000 PLD Gates / 384 Macrocells

— Up to 288 I/O Pins

— 384 Registers

— High-Speed Global Interconnect

— SuperWIDE 32 Generic Logic Block (GLB) Size for

Optimum Performance

— SuperWIDE Input Gating (68 Inputs) for Fast

Counters, State Machines, Address Decoders, etc.

— PCB Efficient Ball Grid Array (BGA) Package Options

— Interfaces with Standard 5V TTL Devices

Global Routing Pool

(GRP)

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 7.5 ns Propagation Delay

— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,

tsu3 (CLK2/3) = 3.5ns

— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels

— Electrically Erasable and Reprogrammable

— Non-Volatile

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Input Bus

— Programmable Speed/Power Logic Path Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

ispLSI 5000V Description

The ispLSI 5000V Family of In-System Programmable

High Density Logic Devices is based on Generic Logic

Blocks (GLBs) of 32 registered macrocells and a single

Global Routing Pool (GRP) structure interconnecting the

GLBs.

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

3.3V IN-SYSTEM PROGRAMMABLE

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture with Single-

Level Global Routing Pool and SuperWIDE GLBs

— Wrap Around Product Term Sharing Array Supports

up to 35 Product Terms Per Macrocell

— Macrocells Support Concurrent Combinatorial and

Registered Functions

— Macrocell Registers Feature Multiple Control

Options Including Set, Reset and Clock Enable

— Four Dedicated Clock Input Pins Plus Macrocell

Product Term Clocks

— Slew and Skew Programmable I/O (SASPI/O)

Supports Programmable Bus Hold, Pull-up, Open

Drain and Slew and Skew Rate Options

Outputs from the GLBs drive the Global Routing Pool

(GRP) between the GLBs. Switching resources are pro-

vided to allow signals in the Global Routing Pool to drive

any or all the GLBs in the device. This mechanism allows

fast, efficient connections across the entire device.

Each GLB contains 32 macrocells and a fully populated,

programmable AND-array with 160 logic product terms

and five extra control product terms. The GLB has 68

inputs from the Global Routing Pool which are available

in both true and complement form for every product term.

The 160 product terms are grouped in 32 sets of five and

sent into a Product Term Sharing Array (PTSA) which

allows sharing up to a maximum of 35 product terms for

a single function. Alternatively, the PTSA can be by-

passed for functions of five product terms or less. The

— Six Global Output Enable Terms, Two Global OE

Pins and One Product Term OE per Macrocell

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

January 2002

5384va_08

12 3 4 5 6 7...31

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与ISPLSI5384VA-70LB388I相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI5384VA-70LQ208	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE⑩ High D
ISPLSI5384VE-100LB272	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDEâ¢ High
ISPLSI5384VE-100LB272I	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDEâ¢ High
ISPLSI5384VE-100LF256	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDEâ¢ High
ISPLSI5384VE-100LF256I	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDEâ¢ High
ISPLSI5384VE-125LB272	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDEâ¢ High
ISPLSI5384VE-125LB272I	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDEâ¢ High
ISPLSI5384VE-125LF256	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDEâ¢ High
ISPLSI5384VE-125LF256I	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDEâ¢ High
ISPLSI5384VE-165LB272	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDEâ¢ High

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