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ISPLSI2192VE-180LT128I

更新时间： 2024-11-18 20:32:03
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
15页 156K
描述
EE PLD, 7.5ns, 192-Cell, CMOS, PQFP128, TQFP-128

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ISPLSI2192VE-180LT128I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-128针数：128
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.82
其他特性：YES最大时钟频率：125 MHz
系统内可编程：YESJESD-30 代码：S-PQFP-G128
JESD-609代码：e0JTAG BST：YES
长度：14 mm湿度敏感等级：3
专用输入次数：5I/O 线路数量：96
宏单元数：192端子数量：128
最高工作温度：85 °C最低工作温度：-40 °C
组织：5 DEDICATED INPUTS, 96 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP128,.64SQ,16封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：240
电源：3.3 V可编程逻辑类型：EE PLD
传播延迟：7.5 ns认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Programmable Logic Devices
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.4 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

ISPLSI2192VE-180LT128I 数据手册

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Lead-  
ee  
®
Fr  
Packag  
Options  
ailable!  
ispLSI 2192VE  
e
3.3V In-System Programmable  
SuperFAST™ High Density PLD  
Av  
Features  
Functional Block Diagram  
• SuperFAST HIGH DENSITY IN-SYSTEM  
PROGRAMMABLE LOGIC  
Output Routing Pool  
Output Routing Pool  
— 8000 PLD Gates  
F7 F6 F5 F4 F3 F2 F1 F0  
E7 E6 E5 E4 E3 E2 E1 E0  
— 96 I/O Pins, Nine or Twelve Dedicated Inputs  
— 192 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
D
D
D
D
Q
Q
Q
Q
Logic  
Array  
Global Routing Pool (GRP)  
GLB  
— Pinout Compatible with ispLSI 2096V and 2096VE  
• 3.3V LOW VOLTAGE ARCHITECTURE  
— Interfaces with Standard 5V TTL Devices  
B0 B1 B2 B3 B4 B5 B6 B7  
Output Routing Pool  
C0 C1 C2 C3 C4 C5 C6 C7  
Output Routing Pool  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 225MHz Maximum Operating Frequency  
— tpd = 4.0ns Propagation Delay  
0139/2192VE  
Description  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
The ispLSI 2192VE is a High Density Programmable  
Logic Device containing 192 Registers, nine or twelve  
Dedicated Input pins, three Dedicated Clock Input pins,  
two dedicated Global OE input pins and a Global Routing  
Pool(GRP). TheGRPprovidescompleteinterconnectivity  
between all of these elements. The ispLSI 2192VE  
features in-system programmability through the Bound-  
ary Scan Test Access Port (TAP) and is 100% IEEE  
1149.1 Boundary Scan Testable. The ispLSI 2192VE  
offers non-volatile reprogrammability of the logic, as well  
as the interconnect to provide truly reconfigurable sys-  
tems.  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
• IN-SYSTEM PROGRAMMABLE  
— 3.3V In-System Programmability (ISP™) Using  
Boundary Scan Test Access Port (TAP)  
— Open-Drain Output Option for Flexible Bus Interface  
Capability, Allowing Easy Implementation of Wired-  
OR Bus Arbitration Logic  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE  
The basic unit of logic on the ispLSI 2192VE device is the  
Generic Logic Block (GLB). The GLBs are labeled A0, A1  
.. F7 (see Figure 1). There are a total of 48 GLBs in the  
ispLSI 2192VE device. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
• THE EASE OF USE AND FAST SYSTEM SPEED OF  
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
• LEAD-FREE PACKAGE OPTIONS  
Copyright©2004LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2004  
2192ve_10  
1
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ISPLSI2192VE-180LT128I 替代型号

型号 品牌 替代类型 描述 数据表
ISPLSI2192VE-180LTN128I LATTICE

完全替代

 EE PLD, 7.5ns, 192-Cell, CMOS, PQFP128, LEAD FREE, TQFP-128
ISPLSI2192VE-100LT128 LATTICE

完全替代

 EE PLD, 13ns, 192-Cell, CMOS, PQFP128, TQFP-128
ISPLSI2192VE-135LT128 LATTICE

完全替代

 3.3V In-System Programmable SuperFAST⑩ High D

与ISPLSI2192VE-180LT128I相关器件

型号 品牌 获取价格 描述 数据表
ISPLSI2192VE180LTN128 LATTICE

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 		3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-180LTN128 LATTICE

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 		EE PLD, 7.5ns, CMOS, PQFP128, TQFP-128
ISPLSI2192VE180LTN128I LATTICE

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 		3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-180LTN128I LATTICE

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 		EE PLD, 7.5ns, 192-Cell, CMOS, PQFP128, LEAD FREE, TQFP-128
ISPLSI2192VE225LB144 LATTICE

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 		3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-225LB144 LATTICE

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 		EE PLD, 6.2ns, 192-Cell, CMOS, PBGA144, FBGA-144
ISPLSI2192VE-225-LB144 LATTICE

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 		3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE225LB144I LATTICE

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 		3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE225LT128 LATTICE

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 		3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-225LT128 LATTICE

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 		EE PLD, 6.2ns, 192-Cell, CMOS, PQFP128, TQFP-128

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