Datasheet > ISPLSI3192

ISPLSI3192

更新时间： 2024-10-29 05:11:51

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑
页数	文件大小	规格书
15页	156K
描述
High Density Programmable Logic

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ISPLSI3192 数据手册

ispLSI 3192

High Density Programmable Logic

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 192 I/O Pins

— 9000 PLD Gates

ORP

F3 F2

ORP

F1 F0

ORP

E3 E2 E1 E0

ORP

Boundary

Scan

— 384 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Global Routing Pool

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 100 MHz Maximum Operating Frequency

— tpd = 10 ns Propagation Delay

Array

Twin

GLB

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

Array

• IN-SYSTEM PROGRAMMABLE

— Supports ISP™ or ispJTAG™ Programming

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

C1 C2

ORP

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

0139/3192

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

Description

The ispLSI 3192 is a High Density Programmable Logic

Device containing 384 Registers, 192 Universal I/O pins,

five Dedicated Clock Input Pins, twelve Output Routing

Pools (ORP), and a Global Routing Pool (GRP) which

allows complete inter-connectivity between all of these

elements. The ispLSI 3192 features 5-Volt in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3192 offers non-volatile reprogrammability of

the logic, as well as the interconnect to provide truly

reconfigurable systems.

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

mize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

The basic unit of logic on the ispLSI 3192 device is the

TwinGenericLogicBlock(TwinGLB)labelledA0,A1...F3.

There are a total of 24 of these Twin GLBs in the ispLSI

3192 device. Each Twin GLB has 24 inputs, a program-

mable AND array and two OR/Exclusive-OR Arrays, and

eight outputs which can be configured to be either com-

binatorial or registered. All Twin GLB inputs come from

the GRP.

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

June 2002

3192_08

12 3 4 5 6 7...15

中文翻译

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与ISPLSI3192相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI3192-100LB272	LATTICE	获取价格	High Density Programmable Logic
ISPLSI3192-100LB272I	LATTICE	获取价格	High Density Programmable Logic
ISPLSI3192-100LM	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI3192-100LQ	LATTICE	获取价格	High Density Programmable Logic
ISPLSI3192-100LQI	LATTICE	获取价格	High Density Programmable Logic
ISPLSI3192-70LB	LATTICE	获取价格	EE PLD, 18ns, CMOS, PBGA272, 27 X 27 MM, BGA-272
ISPLSI3192-70LB272	LATTICE	获取价格	High Density Programmable Logic
ISPLSI3192-70LB272I	LATTICE	获取价格	High Density Programmable Logic
ISPLSI3192-70LBI	LATTICE	获取价格	EE PLD, 18ns, CMOS, PBGA272, 27 X 27 MM, BGA-272
ISPLSI3192-70LM	ETC	获取价格	Electrically-Erasable Complex PLD

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