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ISPLSI3160-70LQ PDF预览

ISPLSI3160-70LQ

更新时间: 2024-10-28 23:59:51
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ISPLSI3160-70LQ 数据手册

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®
ispLSI 3160  
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• HIGH-DENSITY PROGRAMMABLE LOGIC  
— 160 I/O Pins  
— 7000 PLD Gates  
ISP and  
Boundary  
Scan TAP  
ORP  
ORP  
— 320 Registers  
E3  
E2  
E1  
E0  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
A0  
A1  
A2  
A3  
D
D
D
D
Q
D3  
D2  
D1  
D0  
Q
Q
Q
OR  
Array  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
fmax = 125 MHz Maximum Operating Frequency  
tpd = 7.5 ns Propagation Delay  
Twin  
GLB  
D
D
D
D
Q
Q
Q
Q
OR  
Array  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
B0  
B1  
B2  
B3  
C3  
C2  
C1  
C0  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
Global Routing Pool  
(GRP)  
• IN-SYSTEM PROGRAMMABLE  
— 5V In-System Programmability (ISP™) Using  
Lattice ISP or Boundary Scan Test (IEEE 1149.1)  
Protocol  
— Increased Manufacturing Yields, Reduced Time-to-  
Market, and Improved Product Quality  
— Reprogram Soldered Devices for Faster Debugging  
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE  
Description  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
The ispLSI 3160 is a High-Density Programmable Logic  
Devices containing 320 Registers, 160 Universal I/O  
pins, fiveDedicatedClockInputPins, fiveOutputRouting  
Pools (ORP) and a Global Routing Pool (GRP) which  
allows complete inter-connectivity between all of these  
elements. The ispLSI 3160 features 5V in-system pro-  
grammability and in-system diagnostic capabilities. The  
ispLSI 3160 offers non-volatile reprogrammability of the  
logic, as well as the interconnect to provide truly  
reconfigurable systems.  
— Five Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to Mini-  
mize Switching Noise  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
The basic unit of logic on the ispLSI 3160 device is the  
TwinGenericLogicBlock(TwinGLB)labelledA0,A1...E3.  
There are a total of 20 of these Twin GLBs in the ispLSI  
3160 device. Each Twin GLB has 24 inputs, a program-  
mable AND array and two OR/Exclusive-OR Arrays, and  
eight outputs which can be configured to be either com-  
binatorial or registered. All Twin GLB inputs come from  
the GRP.  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Copyright©1999LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
May 1999  
3160_08  
1

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