Datasheet > 暂无类别数据> ISPLSI2128VL-135LT176

ISPLSI2128VL-135LT176

更新时间： 2024-11-17 22:25:11

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
17页	215K
描述
2.5V In-System Programmable SuperFAST⑩ High Density PLD

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ISPLSI2128VL-135LT176 数据手册

浏览型号ISPLSI2128VL-135LT176的Datasheet PDF文件第2页

浏览型号ISPLSI2128VL-135LT176的Datasheet PDF文件第3页

浏览型号ISPLSI2128VL-135LT176的Datasheet PDF文件第4页

浏览型号ISPLSI2128VL-135LT176的Datasheet PDF文件第5页

浏览型号ISPLSI2128VL-135LT176的Datasheet PDF文件第6页

ispLSI 2128VL

2.5V In-System Programmable

SuperFAST™ High Density PLD

Features

Functional Block Diagram*

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

Output Routing Pool (ORP)

D7 D6

Output Routing Pool (ORP)

— 6000 PLD Gates

— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs

— 128 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2128V and 2128VE Devices

Logic

Array

GLB

• 2.5V LOW VOLTAGE 2128 ARCHITECTURE

— Interfaces with Standard 3.3V Devices (Inputs and

I/Os are 3.3V Tolerant)

— 125 mA Typical Active Current

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

Global Routing Pool (GRP)

— fmax = 150 MHz Maximum Operating Frequency

— tpd = 6.0 ns Propagation Delay

Output Routing Pool (ORP)

— Electrically Erasable and Reprogrammable

— Non-Volatile

0139A/2128VL

*128 I/O version shown

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

Description

• IN-SYSTEM PROGRAMMABLE

The ispLSI 2128VL is a High Density Programmable

Logic Device available in 128 and 64 I/O-pin versions.

The device contains 128 Registers, eight Dedicated

Input pins, three Dedicated Clock Input pins, two dedi-

cated Global OE input pins and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 2128VL fea-

tures in-system programmability through the Boundary

Scan Test Access Port (TAP) and is 100% IEEE 1149.1

Boundary Scan Testable. The ispLSI 2128VL offers non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

— 2.5V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

The basic unit of logic on the ispLSI 2128VL device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128VL device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

2128vL_02

12 3 4 5 6 7...17

中文翻译

下载PDF

与ISPLSI2128VL-135LT176相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2128VL-135LT176I	LATTICE	获取价格	2.5V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VL-150LB100	LATTICE	获取价格	2.5V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VL-150LB208	LATTICE	获取价格	2.5V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VL-150LQ160	LATTICE	获取价格	2.5V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VL-150LT100	LATTICE	获取价格	2.5V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VL-150LT176	LATTICE	获取价格	2.5V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE_04	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE100LB144	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-100LB144	LATTICE	获取价格	EE PLD, 13ns, 192-Cell, CMOS, PBGA144, FBGA-144

与ISPLSI2128VL-135LT176相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

17
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

42
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

37

产品中心

服务支持

精选活动

关于我们

帮助中心

ISPLSI2128VL-135LT176

ISPLSI2128VL-135LT176 数据手册

与ISPLSI2128VL-135LT176相关器件

与ISPLSI2128VL-135LT176相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ISPLSI2128VL-135LT176

ISPLSI2128VL-135LT176 数据手册

与ISPLSI2128VL-135LT176相关器件

与ISPLSI2128VL-135LT176相关文章

您还可以找

您在本页遇到什么问题？