Datasheet > ISPLSI2192VE100LB144I

ISPLSI2192VE100LB144I

更新时间： 2024-11-18 02:57:51

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
15页	161K
描述
3.3V In-System Programmable SuperFAST⑩ High Density PLD

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ISPLSI2192VE100LB144I 数据手册

浏览型号ISPLSI2192VE100LB144I的Datasheet PDF文件第2页

浏览型号ISPLSI2192VE100LB144I的Datasheet PDF文件第3页

浏览型号ISPLSI2192VE100LB144I的Datasheet PDF文件第4页

浏览型号ISPLSI2192VE100LB144I的Datasheet PDF文件第5页

浏览型号ISPLSI2192VE100LB144I的Datasheet PDF文件第6页

浏览型号ISPLSI2192VE100LB144I的Datasheet PDF文件第7页

Lead-

Packag

Options

ailable!

ispLSI 2192VE

3.3V In-System Programmable

SuperFAST™ High Density PLD

Features

Functional Block Diagram

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

Output Routing Pool

— 8000 PLD Gates

F7 F6 F5 F4 F3 F2 F1 F0

E7 E6 E5 E4 E3 E2 E1 E0

— 96 I/O Pins, Nine or Twelve Dedicated Inputs

— 192 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Logic

Array

Global Routing Pool (GRP)

GLB

— Pinout Compatible with ispLSI 2096V and 2096VE

• 3.3V LOW VOLTAGE ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 225MHz Maximum Operating Frequency

— tpd = 4.0ns Propagation Delay

0139/2192VE

Description

— Electrically Erasable and Reprogrammable

— Non-Volatile

The ispLSI 2192VE is a High Density Programmable

Logic Device containing 192 Registers, nine or twelve

Dedicated Input pins, three Dedicated Clock Input pins,

two dedicated Global OE input pins and a Global Routing

Pool(GRP). TheGRPprovidescompleteinterconnectivity

between all of these elements. The ispLSI 2192VE

features in-system programmability through the Bound-

ary Scan Test Access Port (TAP) and is 100% IEEE

1149.1 Boundary Scan Testable. The ispLSI 2192VE

offers non-volatile reprogrammability of the logic, as well

as the interconnect to provide truly reconfigurable sys-

tems.

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

The basic unit of logic on the ispLSI 2192VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. F7 (see Figure 1). There are a total of 48 GLBs in the

ispLSI 2192VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• LEAD-FREE PACKAGE OPTIONS

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2004

2192ve_10

12 3 4 5 6 7...15

中文翻译

下载PDF

与ISPLSI2192VE100LB144I相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2192VE-100LT	LATTICE	获取价格	EE PLD, 10ns, CMOS, PQFP128, TQFP-128
ISPLSI2192VE100LT128	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-100LT128	LATTICE	获取价格	EE PLD, 13ns, 192-Cell, CMOS, PQFP128, TQFP-128
ISPLSI2192VE-100-L-T128	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE100LT128I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE100LTN128	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-100LTN128	LATTICE	获取价格	EE PLD, 13ns, 192-Cell, CMOS, PQFP128, LEAD FREE, TQFP-128
ISPLSI2192VE100LTN128I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE135LB144	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-135LB144	LATTICE	获取价格	EE PLD, 10ns, 192-Cell, CMOS, PBGA144, FBGA-144

与ISPLSI2192VE100LB144I相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

17
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

42
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

37

产品中心

服务支持

精选活动

关于我们

帮助中心

ISPLSI2192VE100LB144I

ISPLSI2192VE100LB144I 数据手册

与ISPLSI2192VE100LB144I相关器件

与ISPLSI2192VE100LB144I相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ISPLSI2192VE100LB144I

ISPLSI2192VE100LB144I 数据手册

与ISPLSI2192VE100LB144I相关器件

与ISPLSI2192VE100LB144I相关文章

您还可以找

您在本页遇到什么问题？