Datasheet > ISPLSI2192VE-135LB144

ISPLSI2192VE-135LB144

更新时间： 2024-10-29 14:31:35

品牌	Logo	应用领域
莱迪思 - LATTICE		时钟输入元件可编程逻辑
页数	文件大小	规格书
15页	141K
描述
EE PLD, 10ns, 192-Cell, CMOS, PBGA144, FBGA-144

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ISPLSI2192VE-135LB144 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	FBGA-144	针数：	144
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.82
Is Samacsys：	N	其他特性：	YES
最大时钟频率：	100 MHz	系统内可编程：	YES
JESD-30 代码：	S-PBGA-B144	JESD-609代码：	e0
JTAG BST：	YES	长度：	13 mm
湿度敏感等级：	3	专用输入次数：	8
I/O 线路数量：	96	宏单元数：	192
端子数量：	144	最高工作温度：	70 °C
最低工作温度：		组织：	8 DEDICATED INPUTS, 96 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA144,12X12,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	240	电源：	3.3 V
可编程逻辑类型：	EE PLD	传播延迟：	10 ns
认证状态：	Not Qualified	座面最大高度：	2.1 mm
子类别：	Programmable Logic Devices	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	13 mm	Base Number Matches：	1

ISPLSI2192VE-135LB144 数据手册

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ispLSI 2192VE

3.3V In-System Programmable

SuperFAST™ High Density PLD

Features

Functional Block Diagram

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

Output Routing Pool

— 8000 PLD Gates

F7 F6 F5 F4 F3 F2 F1 F0

E7 E6 E5 E4 E3 E2 E1 E0

— 96 I/O Pins, Nine or Twelve Dedicated Inputs

— 192 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Pinout Compatible with ispLSI 2096V and 2096VE

Logic

Array

Global Routing Pool (GRP)

GLB

• 3.3V LOW VOLTAGE ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 225MHz* Maximum Operating Frequency

— tpd = 4.0ns* Propagation Delay

0139/2192VE

Description

— Electrically Erasable and Reprogrammable

— Non-Volatile

The ispLSI 2192VE is a High Density Programmable

Logic Device containing 192 Registers, nine or twelve

Dedicated Input pins, three Dedicated Clock Input pins,

two dedicated Global OE input pins and a Global Routing

Pool(GRP). TheGRPprovidescompleteinterconnectivity

between all of these elements. The ispLSI 2192VE

features in-system programmability through the Bound-

ary Scan Test Access Port (TAP) and is 100% IEEE

1149.1 Boundary Scan Testable. The ispLSI 2192VE

offers non-volatile reprogrammability of the logic, as well

as the interconnect to provide truly reconfigurable sys-

tems.

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

The basic unit of logic on the ispLSI 2192VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. F7 (see Figure 1). There are a total of 48 GLBs in the

ispLSI 2192VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

*Preliminary

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2000

2192ve_06

12 3 4 5 6 7...15

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与ISPLSI2192VE-135LB144相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2192VE-135-LB144	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE135LB144I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-135LT	LATTICE	获取价格	EE PLD, 7.5ns, CMOS, PQFP128, TQFP-128
ISPLSI2192VE135LT128	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-135LT128	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-135-L-T128	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE135LT128I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE135LTN128	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-135LTN128	LATTICE	获取价格	EE PLD, 10ns, 192-Cell, CMOS, PQFP128, LEAD FREE, TQFP-128
ISPLSI2192VE135LTN128I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D

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