Datasheet > 可编程逻辑 > 可编程逻辑器件> ISPLSI2128VL-150LB100

ISPLSI2128VL-150LB100

更新时间： 2024-10-28 22:07:47

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
17页	215K
描述
2.5V In-System Programmable SuperFAST⑩ High Density PLD

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ISPLSI2128VL-150LB100 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	CABGA-100
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.75	Is Samacsys：	N
其他特性：	YES	最大时钟频率：	111 MHz
系统内可编程：	YES	JESD-30 代码：	S-PBGA-B100
JESD-609代码：	e0	JTAG BST：	YES
长度：	10 mm	湿度敏感等级：	3
专用输入次数：	4	I/O 线路数量：	64
宏单元数：	128	端子数量：	100
最高工作温度：	70 °C	最低工作温度：
组织：	4 DEDICATED INPUTS, 64 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装等效代码：	BGA100,10X10,32	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	240
电源：	2.5 V	可编程逻辑类型：	EE PLD
传播延迟：	8.5 ns	认证状态：	Not Qualified
座面最大高度：	1.5 mm	子类别：	Programmable Logic Devices
最大供电电压：	2.7 V	最小供电电压：	2.3 V
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	10 mm
Base Number Matches：	1

ISPLSI2128VL-150LB100 数据手册

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ispLSI 2128VL

2.5V In-System Programmable

SuperFAST™ High Density PLD

Features

Functional Block Diagram*

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

Output Routing Pool (ORP)

D7 D6

Output Routing Pool (ORP)

— 6000 PLD Gates

— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs

— 128 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2128V and 2128VE Devices

Logic

Array

GLB

• 2.5V LOW VOLTAGE 2128 ARCHITECTURE

— Interfaces with Standard 3.3V Devices (Inputs and

I/Os are 3.3V Tolerant)

— 125 mA Typical Active Current

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

Global Routing Pool (GRP)

— fmax = 150 MHz Maximum Operating Frequency

— tpd = 6.0 ns Propagation Delay

Output Routing Pool (ORP)

— Electrically Erasable and Reprogrammable

— Non-Volatile

0139A/2128VL

*128 I/O version shown

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

Description

• IN-SYSTEM PROGRAMMABLE

The ispLSI 2128VL is a High Density Programmable

Logic Device available in 128 and 64 I/O-pin versions.

The device contains 128 Registers, eight Dedicated

Input pins, three Dedicated Clock Input pins, two dedi-

cated Global OE input pins and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 2128VL fea-

tures in-system programmability through the Boundary

Scan Test Access Port (TAP) and is 100% IEEE 1149.1

Boundary Scan Testable. The ispLSI 2128VL offers non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

— 2.5V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

The basic unit of logic on the ispLSI 2128VL device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128VL device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

2128vL_02

12 3 4 5 6 7...17

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与ISPLSI2128VL-150LB100相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2128VL-150LB208	LATTICE	获取价格	2.5V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VL-150LQ160	LATTICE	获取价格	2.5V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VL-150LT100	LATTICE	获取价格	2.5V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VL-150LT176	LATTICE	获取价格	2.5V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE_04	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE100LB144	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE-100LB144	LATTICE	获取价格	EE PLD, 13ns, 192-Cell, CMOS, PBGA144, FBGA-144
ISPLSI2192VE-100-LB144	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2192VE100LB144I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D

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