Datasheet > ISPLSI1032E80LJNI

ISPLSI1032E80LJNI

更新时间： 2024-11-14 05:11:51

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
17页	295K
描述
In-System Programmable High Density PLD

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Lead-

Package

Options

ispLSI 1032E

vailable!

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH DENSITY PROGRAMMABLE LOGIC

— 6000 PLD Gates

Output Routing Pool

— 64 I/O Pins, Eight Dedicated Inputs

— 192 Registers

D7 D6 D5 D4 D3 D2 D1 D0

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

Logic

Array

GLB

— Small Logic Block Size for Random Logic

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 7.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

Global Routing Pool (GRP)

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

CLK

0139A(A1)-isp

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

Description

• IN-SYSTEM PROGRAMMABLE

The ispLSI 1032E is a High Density Programmable Logic

Device containing 192 Registers, 64 Universal I/O pins,

eight Dedicated Input pins, four Dedicated Clock Input

pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 1032E device offers 5V non-vola-

tile in-system programmability of the logic, as well as the

interconnects to provide truly reconfigurable systems. A

functional superset of the ispLSI 1032 architecture, the

ispLSI 1032E device adds two new global output enable

pins.

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

The basic unit of logic on the ispLSI 1032E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…D7(seeFigure1). Thereareatotalof32GLBsinthe

ispLSI 1032E device. Each GLB has 18 inputs, a pro-

grammableAND/OR/ExclusiveORarray,andfouroutputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any GLB on the device.

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

— Lead-Free Package Options

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2006

1032e_09

12 3 4 5 6 7...17

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与ISPLSI1032E80LJNI相关器件

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ISPLSI1032E-90LJ	LATTICE	获取价格	In-System Programmable High Density PLD
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