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ISPLSI1032EA-100LT100 PDF预览

ISPLSI1032EA-100LT100

更新时间： 2024-11-13 22:11:43
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
16页 199K
描述
In-System Programmable High Density PLD

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ISPLSI1032EA-100LT100 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.83
Is Samacsys：N其他特性：YES
最大时钟频率：77 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G100JESD-609代码：e0
JTAG BST：YES长度：14 mm
湿度敏感等级：3专用输入次数：2
I/O 线路数量：64宏单元数：128
端子数量：100最高工作温度：70 °C
最低工作温度：组织：2 DEDICATED INPUTS, 64 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP100,.63SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：240电源：3.3/5,5 V
可编程逻辑类型：EE PLD传播延迟：10 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

ISPLSI1032EA-100LT100 数据手册

 浏览型号ISPLSI1032EA-100LT100的Datasheet PDF文件第2页浏览型号ISPLSI1032EA-100LT100的Datasheet PDF文件第3页浏览型号ISPLSI1032EA-100LT100的Datasheet PDF文件第4页浏览型号ISPLSI1032EA-100LT100的Datasheet PDF文件第5页浏览型号ISPLSI1032EA-100LT100的Datasheet PDF文件第6页浏览型号ISPLSI1032EA-100LT100的Datasheet PDF文件第7页 
®
ispLSI 1032EA  
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• HIGH DENSITY PROGRAMMABLE LOGIC  
— 6000 PLD Gates  
Output Routing Pool  
— 64 I/O Pins, Four Dedicated Inputs  
— 192 Registers  
D7 D6 D5 D4 D3 D2 D1 D0  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
— Functionally Compatible with ispLSI 1032E  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
C7  
C6  
C5  
C4  
C3  
C2  
C1  
C0  
D
D
D
D
Q
Q
Q
Q
Logic  
Array  
GLB  
• NEW FEATURES  
— 100% IEEE 1149.1 Boundary Scan Testable  
— ispJTAG™ In-System Programmable via IEEE 1149.1  
(JTAG) Test Access Port  
— User Selectable 3.3V or 5V I/O Supports Mixed-  
Voltage Systems (VCCIO Pin)  
— Open-Drain Output Option  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
Global Routing Pool (GRP)  
B0 B1 B2 B3 B4 B5 B6 B7  
Output Routing Pool  
CLK  
— fmax = 200 MHz Maximum Operating Frequency  
— tpd = 4.5 ns Propagation Delay  
0139A/1032EA  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
Description  
The ispLSI 1032EA is a High Density Programmable  
Logic Device containing 192 Registers, 64 Universal I/O  
pins, four Dedicated Input pins, four Dedicated Clock  
Input pins and a Global Routing Pool (GRP). The GRP  
provides complete interconnectivity between all of these  
elements. The ispLSI 1032EA features 5V in-system  
programmability (ISP™) and in-system diagnostic capa-  
bilities via IEEE 1149.1 Test Access Port. The ispLSI  
1032EA device offers non-volatile reprogrammability of  
the logic, as well as the interconnects to provide truly  
reconfigurable systems. A functional superset of the  
ispLSI1032architecture, theispLSI1032EAdeviceadds  
user selectable 3.3V or 5V I/O and open-drain output  
options.  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
• IN-SYSTEM PROGRAMMABLE  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Four Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to  
Minimize Switching Noise  
The basic unit of logic on the ispLSI 1032EA device is the  
Generic Logic Block (GLB). The GLBs are labeled A0,  
A1…D7 (Figure 1). There are a total of 32 GLBs in the  
ispLSI 1032EA device. Each GLB has 18 inputs, a  
programmable AND/OR/Exclusive OR array, and four  
outputs which can be configured to be either combinato-  
rial or registered. Inputs to the GLB come from the GRP  
and dedicated inputs. All of the GLB outputs are brought  
back into the GRP so that they can be connected to the  
inputs of any other GLB on the device.  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Copyright©2000LatticeSemiconductorCorp.Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
June 2000  
1032ea_03  
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ISPLSI1032EA-100LT100 替代型号

型号 品牌 替代类型 描述 数据表
ISPLSI1032EA-200LT100 LATTICE

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