®
®
ispLSI and pLSI 1016E
High-Density Programmable Logic
Features
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— High-Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
A0
A1
A2
A3
A4
A5
A6
A7
B7
B6
B5
B4
B3
B2
B1
B0
D
D
D
D
Q
Q
Q
Q
Logic
Array
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
GLB
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
Global Routing Pool (GRP)
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
CLK
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
0139C1-isp
Description
— Reprogram Soldered Device for Faster Prototyping
The ispLSI and pLSI 1016E are High-Density
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY Programmable Logic Devices containing 96 Registers,
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
32 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins, one Global OE input pin and
aGlobalRoutingPool(GRP).TheGRPprovidescomplete
interconnectivity between all of these elements. The
ispLSI 1016E features 5-Volt in-system programming
and in-system diagnostic capabilities. The ispLSI 1016E
offers non-volatile “on-the-fly” reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems. It is architecturally and
parametrically compatible to the pLSI 1016E device, but
multiplexes four input pins to control in-system
programming. A functional superset of the ispLSI and
pLSI 1016 architecture, the ispLSI and pLSI 1016E
devices add a new global output enable pin.
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• pLSI/ispLSI DEVELOPMENT TOOLS
pDS® Software
— Easy to Use PC Windows™ Interface
— Boolean Logic Compiler
— Manual Partitioning
The basic unit of logic on the ispLSI and pLSI 1016E
devices is the Generic Logic Block (GLB). The GLBs are
labeled A0, A1...B7 (see figure 1). There are a total of 16
GLBs in the ispLSI and pLSI 1016E devices. Each GLB
has 18 inputs, a programmable AND/OR/Exclusive OR
array, and four outputs which can be configured to be
either combinatorial or registered. Inputs to the GLB
come from the GRP and dedicated inputs. All of the GLB
outputs are brought back into the GRP so that they can
be connected to the inputs of any other GLB on the
device.
— Automatic Place and Route
— Static Timing Table
ispDS+™ Software
— Industry Standard, Third-Party Design
Environments
— Schematic Capture, State Machine, HDL
— Automatic Partitioning and Place and Route
— Comprehensive Logic and Timing Simulation
— PC and Workstation Platforms
Copyright©1997LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
February 1997
1996 ISP Encyclopedia
1016E_04
5秒后页面跳转
SL74HC10N：高性能三输入与非门解析
AIC1781A 电池充电控制器深度解析
Pickering新高压舌簧继电器亮相汽车测试博览会
采用MCU+MPU双处理器架构实现的创新应用设计探索
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
