Datasheet > ISL6615A

ISL6615A

更新时间： 2025-09-19 14:58:15

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
13页	680K
描述
High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features

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ISL6615A 数据手册

ISL6615A

Description

PWM

1.18V < PWM < 2.36V

0.76V < PWM < 1.96V

PDLU

PDHU

TSSHD

PDTS

UGATE

LGATE

TSSHD

PDLL

PDHL

FIGURE 1. TIMING DIAGRAM

lower MOSFETs from conducting simultaneously. This is

accomplished by ensuring the rising gate turns on its MOSFET

with minimum and sufficient delay after the other has turned off.

Operation

Designed for versatility and speed, the ISL6615A MOSFET driver

controls both high-side and low-side N-Channel FETs of a half-

bridge power train from one externally provided PWM signal.

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it drops below 1.75V. Prior to reaching this level,

there is a 25ns blanking period to protect against sudden dips in

the LGATE voltage. Once 1.75V is reached, the UGATE is released

to rise after 20ns of propagation delay. Once the PHASE is high,

the adaptive shoot-through circuitry monitors the PHASE and

UGATE voltages during PWM falling edge and subsequent UGATE

turn-off. If PHASE falls to less than +0.8V, the LGATE is released

to turn on after 10ns of propagation delay. If the UGATE-PHASE

falls to less than 1.75V and after 40ns of propagation delay,

LGATE is released to rise.

Prior to VCC exceeding its POR level, the Pre-POR overvoltage

protection function is activated during initial start-up; the upper

gate (UGATE) is held low and the lower gate (LGATE), controlled

by the Pre-POR overvoltage protection circuits, is connected to

the PHASE. Once the VCC voltage surpasses the VCC Rising

Threshold (see “Electrical Specifications” on page 4) the PWM

signal takes control of gate transitions. A rising edge on PWM

initiates the turn-off of the lower MOSFET (see “TIMING

DIAGRAM” on page 6). After a short propagation delay [t

the lower gate begins to fall. Typical fall times [t ] are provided

PDLL

in the “Electrical Specifications” on page 4. Adaptive shoot-

through circuitry monitors the LGATE voltage and determines the

Tri-state PWM Input

A unique feature of these drivers and other Intersil drivers is the

addition of a shutdown window to the PWM input. If the PWM

signal enters and remains within the shutdown window for a set

holdoff time, the driver outputs are disabled and both MOSFET

gates are pulled and held low. The shutdown state is removed

when the PWM signal moves outside the shutdown window.

Otherwise, the PWM rising and falling thresholds outlined in

“Electrical Specifications” on page 4, determine when the lower

and upper gates are enabled.

upper gate delay time [t

]. This prevents both the lower and

upper MOSFETs from conducting simultaneously. Once this delay

PDHU

period is complete, the upper gate drive begins to rise [t ] and

the upper MOSFET turns on.

A falling transition on PWM results in the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

propagation delay [t

] is encountered before the upper gate

PDLU

begins to fall [t ]. Again, the adaptive shoot-through circuitry

determines the lower gate delay time, t

. The PHASE voltage

PDHL

This feature helps prevent a negative transient on the output

voltage when the output is shut down, eliminating the Schottky

diode that is used in some systems for protecting the load from

reversed output voltage events.

and the UGATE voltage are monitored, and the lower gate is

allowed to rise after PHASE drops below a level or the voltage of

UGATE to PHASE reaches a level depending upon the current

direction (See the following section titled “Advanced Adaptive

Zero Shoot-Through Dead-Time Control” for details). The lower

In addition, more than 400mV hysteresis also incorporates into

the Tri-State shutdown window to eliminate PWM input

oscillations due to the capacitive load seen by the PWM input

through the body diode of the controller’s PWM output when the

power-up and/or power-down sequence of bias supplies of the

driver and PWM controller are required.

gate then rises [t ], turning on the lower MOSFET.

Advanced Adaptive Zero Shoot-Through

Dead-time Control

The ISL6615A driver incorporates a unique adaptive dead-time

control technique to minimize dead-time, resulting in high

efficiency from the reduced freewheeling time of the lower

MOSFETs’ body-diode conduction, and to prevent the upper and

FN6608 Rev 2.00

April 13, 2012

Page 6 of 13

1...3 4 567 8 9...13

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与ISL6615A相关器件

型号	品牌	获取价格	描述	数据表
ISL6615ACBZ	INTERSIL	获取价格	High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features
ISL6615ACBZ	RENESAS	获取价格	最小供电电压(V):6.8V;最大供电电压(V):13.2V;峰值输出灌电流(A):2.5
ISL6615ACBZ-T	RENESAS	获取价格	6A AND GATE BASED MOSFET DRIVER, PDSO8, ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8
ISL6615ACRZ	INTERSIL	获取价格	High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features
ISL6615ACRZ	RENESAS	获取价格	High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features; DFN10, SOIC8;
ISL6615ACRZ-T	RENESAS	获取价格	High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features; DFN10, SOIC8;
ISL6615ACRZ-T13	RENESAS	获取价格	AND GATE BASED MOSFET DRIVER
ISL6615AFRZ	INTERSIL	获取价格	High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features
ISL6615AFRZ	RENESAS	获取价格	AND GATE BASED MOSFET DRIVER, PDSO10, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, DFN-10
ISL6615AFRZ-T	RENESAS	获取价格	AND GATE BASED MOSFET DRIVER, PDSO10, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, DFN-10

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