®
IS93C56A
IS93C66A
ISSI
Write Enable (WEN)
Write All (WRALL)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done. When Vcc is applied,
this device powers up in the write disabled state. The
devicethenremainsinawritedisabledstateuntilaWEN
instruction is executed. Thereafter, the device remains
enabled until a WDS instruction is executed or until Vcc
is removed. (See Figure 4.) (Note: Chip select must
remain LOW until Vcc reaches its operational value.)
The write all (WRALL) instruction programs all registers
withthedatapatternspecifiedintheinstruction.Aswiththe
WRITE instruction, the falling edge of CS must occur to
initiate the self-timed programming cycle. If CS is then
broughtHIGHafteraminimumwaitof200ns(tCS),theDOUT
pin indicates the READY/BUSY status of the chip (see
Figure 6). Vcc is required to be above 4.5V for WRALL to
function properly.
Write Disable (WDS)
Write (WRITE)
The write disable (WDS) instruction disables all programming
capabilities. This protects the entire device against acci-
dental modification of data until a WEN instruction is
executed. (When Vcc is applied, this part powers up in the
write disabled state.) To protect data, a WDS instruction
should be executed upon completion of each programming
operation.
TheWRITEinstructionincludes8or16bitsofdatatobe
written into the specified register. After the last data bit
has been applied to DIN, and before the next rising edge
of SK, CS must be brought LOW. If the device is write-
enabled, then the falling edge of CS initiates the self-
timed programming cycle (see WEN).
IfCSisbroughtHIGH,afteraminimumwaitof200ns(5V
operation) after the falling edge of CS (tCS) DOUT will
indicatetheREADY/BUSYstatusofthechip.Logical“0”
meansprogrammingisstillinprogress;logical“1”means
the selected register has been written, and the part is
readyforanotherinstruction(seeFigure5).TheREADY/
BUSYstatuswillnotbeavailableif:a)TheCSinputgoes
HIGHaftertheendoftheself-timedprogrammingcycle,
tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and
SK goes HIGH, which clears the status flag.
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought
LOW.ThefallingedgeofCSinitiatestheself-timedinternal
programming cycle. Bringing CS HIGH after a minimum of
tCS, will cause DOUT to indicate the READ/BUSY status of the
chip:alogical“0”indicatesprogrammingisstillinprogress;
a logical “1” indicates the erase cycle is complete and the
part is ready for another instruction (see Figure 8).
Erase All (ERAL)
Fullchiperaseisprovidedforeaseofprogramming.Erasing
the entire chip involves setting all bits in the entire memory
array to a logical “1” (see Figure 9). Vcc is required to be
above 4.5V for ERALL to function properly.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. A
05/02/06
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