Datasheet > IS64VLPS409618B-166M3LA3

IS64VLPS409618B-166M3LA3

更新时间： 2024-12-02 09:16:07

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
38页	1647K
描述
Cache SRAM, 4MX18, 3.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LFBGA-165

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IS64VLPS409618B-166M3LA3 数据手册

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wordsꢀbyꢀ32ꢀbits.

36ꢀbits.ꢀTheꢀIS61LPS204832Bꢀisꢀorganizedꢀasꢀ2,096,952ꢀ

TheꢀIS61LPS/VPS409618Bꢀisꢀorganizedꢀ

IS61LPS409618B, IS61LPS204836B, IS61LPS204832B, IS64LPS204836B,

IS61VPS/VVPS409618B, IS61VPS/VVPS204836B

2M x 36, 2M x 32, 4M x 18

72 Mb SYNCHRONOUS PIPELINED,

ADVANCED INFORMATION

FEBRUARY 2013

SINGLE CYCLE DESELECT STATIC RAM

FEATURES

DESCRIPTION

Theꢀ72Mbꢀproductꢀfamilyꢀfeaturesꢀ high-speed,ꢀlow-powerꢀ

synchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀburstable,ꢀ

high-performanceꢀ memoryꢀ forꢀ communicationꢀ andꢀ net-

workingꢀapplications.ꢀTheꢀIS61LPS/VPS204836Bꢀandꢀ

IS64LPS204836Bꢀareꢀorganizedꢀasꢀ2,096,952ꢀwordsꢀbyꢀ

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ

control

•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ

asꢀ4,193,904ꢀwordsꢀbyꢀ18ꢀbits.ꢀFabricatedꢀwithꢀISSI'sꢀ

advancedꢀ CMOSꢀ technology,ꢀ theꢀ deviceꢀ integratesꢀ aꢀ

2-bitꢀburstꢀcounter,ꢀhigh-speedꢀSRAMꢀcore,ꢀandꢀhigh-

driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀmonolithicꢀcircuit.ꢀAllꢀ

synchronousꢀinputsꢀpassꢀthroughꢀregistersꢀcontrolledꢀbyꢀ

aꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.

•ꢀ Threeꢀchipꢀenableꢀoptionꢀforꢀsimpleꢀdepthꢀex-

pansionꢀandꢀaddressꢀpipelining

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ AutoꢀPower-downꢀduringꢀdeselect

•ꢀ Singleꢀcycleꢀdeselect

Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ

theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀ

oneꢀtoꢀfourꢀbytesꢀwideꢀasꢀcontrolledꢀbyꢀtheꢀwriteꢀcontrolꢀ

inputs.

•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby

•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackage

•ꢀ PowerꢀSupply

Separateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀwritten.ꢀ

Theꢀbyteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀtheꢀbyteꢀ

writeꢀenableꢀ(BWE)ꢀinputꢀcombinedꢀwithꢀoneꢀorꢀmoreꢀ

individualꢀbyteꢀwriteꢀsignalsꢀ(BWx). Inꢀaddition,ꢀGlobalꢀ

Writeꢀ(GW)ꢀisꢀavailableꢀforꢀwritingꢀallꢀbytesꢀatꢀoneꢀtime,ꢀ

regardlessꢀofꢀtheꢀbyteꢀwriteꢀcontrols.

ꢀ LPS:ꢀVdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)

VPS:ꢀVdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)

VVPS:ꢀVdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)

•ꢀ JEDECꢀ100-PinꢀTQFP,ꢀ119-ballꢀPBGA,ꢀandꢀ

165-ballꢀPBGAꢀpackages

BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSPꢀ(AddressꢀStatusꢀ

Processor)ꢀorꢀADSCꢀ(AddressꢀStatusꢀCacheꢀController)ꢀ

inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-

atedꢀinternallyꢀandꢀcontrolledꢀbyꢀtheꢀADVꢀ(burstꢀaddressꢀ

advance)ꢀinputꢀpin.ꢀ

•ꢀ Lead-freeꢀavailable

Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀor-

der,ꢀLinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀ

InterleaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀ

orꢀleftꢀﬂoating.

FAST ACCESS TIME

Symbol

Parameter

250

2.6ꢀ

4ꢀ

200

3.1ꢀ

5ꢀ

166

3.5ꢀ

6ꢀ

Units

ꢀ

tkq

tkc

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

Frequencyꢀ

250ꢀ

200ꢀ

166ꢀ

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00C

2/26/2013

12 3 4 5 6 7...38

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与IS64VLPS409618B-166M3LA3相关器件

型号	品牌	获取价格	描述	数据表
IS64VLPS409618B-166TQ2A3	ISSI	获取价格	Cache SRAM, 4MX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
IS64VPS102436B-166B2LA3	ISSI	获取价格	Cache SRAM, 1MX36, 3.8ns, CMOS, PBGA119, BGA-119
IS64VPS12832A-200TQA3	ISSI	获取价格	128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC R
IS64VPS12832EC-200B2A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12832EC-200B2LA3	ISSI	获取价格	Cache SRAM, 128KX32, 3.1ns, CMOS, PBGA119, BGA-119
IS64VPS12832EC-200B3A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12832EC-200B3LA3	ISSI	获取价格	Cache SRAM, 128KX32, 3.1ns, CMOS, PBGA165, TFBGA-165
IS64VPS12832EC-200TQA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12832EC-200TQLA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12832EC-250B2A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM

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