Datasheet > IS64VPS12836A

IS64VPS12836A

更新时间： 2024-01-03 19:50:58

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
26页	167K
描述
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS64VPS12836A 数据手册

IS61(64)LPS12832A

IS61(64)LPS12836A IS61(64)VPS12836A

IS61(64)LPS25618A IS61(64)VPS25618A

ISSI

128K x 32, 128K x 36, 256K x 18

4 Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

PRELIMINARY INFORMATION

FEBRUARY 2005

DESCRIPTION

FEATURES

The ISSIIS61(64)LPS12832A,IS61(64)LPS/VPS12836A

andIS61(64)LPS/VPS25618Aarehigh-speed,low-power

synchronous static RAMs designed to provide burstable,

high-performancememoryforcommunicationandnetwork-

ingapplications.TheIS61(64)LPS12832Aisorganizedas

131,072wordsby32bits.TheIS61(64)LPS/VPS12836A

isorganizedas131,072wordsby36bits.TheIS61(64)LPS/

VPS25618A is organized as 262,144 words by 18 bits.

Fabricated with ISSI's advanced CMOS technology, the

deviceintegratesa2-bitburstcounter,high-speedSRAM

core,andhigh-drivecapabilityoutputsintoasinglemono-

lithic circuit. All synchronous inputs pass through regis-

ters controlled by a positive-edge-triggered single clock

input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

Write cycles are internally self-timed and are initiated by

therisingedgeoftheclockinput. Writecyclescanbeone

tofourbyteswideascontrolledbythewritecontrolinputs.

• Snooze MODE for reduced-power standby

• Power Supply

Separatebyteenablesallowindividualbytestobewritten.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). In addition, Global

Write (GW) is available for writing all bytes at one time,

regardless of the byte write controls.

LPS: V^DD3.3V + 5%, VDDQ 3.3V/2.5V + 5%

VPS: V^DD2.5V + 5%, VDDQ 2.5V + 5%

• JEDEC 100-Pin TQFP, 119-ball PBGA, and

165-ball PBGA packages

• Automotive temperature available

• Lead Free available

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

inputpins.Subsequentburstaddressescanbegenerated

internally and controlled by the ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

250

2.6

200

3.1

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00A

10/07/04

12 3 4 5 6 7...26

中文翻译

下载PDF

与IS64VPS12836A相关器件

型号	品牌	获取价格	描述	数据表
IS64VPS12836A-200TQA3	ISSI	获取价格	128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC R
IS64VPS12836EC-200B2A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12836EC-200B2LA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12836EC-200B3A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12836EC-200B3LA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12836EC-200TQA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12836EC-200TQLA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12836EC-250B2A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12836EC-250B2LA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS64VPS12836EC-250B3A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM

与IS64VPS12836A相关文章

SL74HC10N：高性能三输入与非门解析
2024-09-03

45
AIC1781A 电池充电控制器深度解析
2024-09-03

33
Pickering新高压舌簧继电器亮相汽车测试博览会
2024-08-26

72
采用MCU+MPU双处理器架构实现的创新应用设计探索
2024-08-23

80

产品中心

服务支持

精选活动

关于我们

帮助中心

IS64VPS12836A

IS64VPS12836A 数据手册

与IS64VPS12836A相关器件

与IS64VPS12836A相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS64VPS12836A

IS64VPS12836A 数据手册

与IS64VPS12836A相关器件

与IS64VPS12836A相关文章

您还可以找

您在本页遇到什么问题？