Datasheet > IS64S6432-100TQA2

IS64S6432-100TQA2

更新时间： 2024-11-30 19:48:39

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器内存集成电路
页数	文件大小	规格书
19页	114K
描述
Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, TQFP-100

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IS64S6432-100TQA2 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TQFP-100	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	5 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	2097152 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	32
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	105 °C	最低工作温度：	-40 °C
组织：	64KX32	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

IS64S6432-100TQA2 数据手册

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IS64S6432

IS64LV6432

ISSI

PRELIMINARYINFORMATION

SEPTEMBER2002

64K x 32 SYNCHRONOUS

PIPELINE STATIC RAM

FEATURES

DESCRIPTION

The ISSI IS64S6432/IS64LV6432 is a high-speed, low-

power synchronous static RAM designed to provide a

burstable, high-performance memory. It is organized as

65,536 words by 32 bits, fabricated with ISSI's advanced

CMOS technology. The device integrates a 2-bit burst

counter, high-speed SRAM core, and high-drive capability

outputs into a single monolithic circuit. All synchronous

inputspassthroughregisterscontrolledbyapositive-edge-

triggered single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 100-Pin TQFP package

• Single +3.3V power supply

Writecyclesareinternallyself-timedandareinitiatedbythe

rising edge of the clock input. Write cycles can be from one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3

controlsDQ17-DQ24,BW4controlsDQ25-DQ32,conditioned

by BWE being LOW. A LOW on GW input would cause all

bytes to be written.

• IS64S6432: 3.3V V^DDQ(I/O Voltage)

• IS64LV6432: 2.5V V^DDQ(I/O Voltage)

• Two Clock enables and one Clock disable to

eliminate multiple bank bus contention

• Control pins mode upon power-up:

– MODE in interleave burst mode

– ZZ in normal operation mode

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internallybytheIS64S6432/IS64LV6432andcontrolledby

the ADV (burst address advance) input pin.

• Temperature offerings:

Option A1: -40^oC to +85^oC

Option A2: -40^oC to +105^oC

Option A3: -40^oC t0 +125^oC

Asynchronous signals include output enable (OE), sleep

modeinput(ZZ),clock(CLK)andburstmodeinput(MODE).

A HIGH input on the ZZ pin puts the SRAM in the power-

down state. When ZZ is pulled LOW (or no connect), the

SRAM normally operates after three cycles of the wake-up

period. A LOW input, i.e., GND^Q, on MODE pin selects

LINEARBurst.AVDDQ (ornoconnect)onMODEpinselects

INTERLEAVED Burst.

FAST ACCESS TIME

Symbol

tKQ

Parameter

CLK Access Time

Cycle Time

-133

-100

Unit

tKC

7.5

133

—

Frequency

100

MHz

Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00A

09/20/02

12 3 4 5 6 7...19

中文翻译

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与IS64S6432-100TQA2相关器件

型号	品牌	获取价格	描述	数据表
IS64S6432-133TQA2	ISSI	获取价格	Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, TQFP-100
IS64S6432-133TQA3	ISSI	获取价格	Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, TQFP-100
IS64VF102436B-7.5TQLA3	ISSI	获取价格	Cache SRAM, 1MX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
IS64VF12832A	ISSI	获取价格	128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS64VF12832A-7.5TQLA3	ISSI	获取价格	128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS64VF12832EC-6.5B2A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64VF12832EC-6.5B2LA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64VF12832EC-6.5B3A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64VF12832EC-6.5B3LA3	ISSI	获取价格	Cache SRAM, 128KX32, 6.5ns, CMOS, PBGA165, TFBGA-165
IS64VF12832EC-6.5TQA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM

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