Datasheet > IS64VF12832A

IS64VF12832A

更新时间： 2024-02-08 12:23:05

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
25页	166K
描述
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS64VF12832A 数据手册

IS61(64)LF12832A IS64VF12832A

IS61(64)LF12836A IS61(64)VF12836A

IS61(64)LF25618A IS61(64)VF25618A

ISSI

128K x 32, 128K x 36, 256K x 18

4 Mb SYNCHRONOUS FLOW-THROUGH

STATIC RAM

PRELIMINARY INFORMATION

AUGUST 2005

DESCRIPTION

FEATURES

The ISSI IS61(64)LF12832A,

IS64VF12832A,

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are

high-speed, low-powersynchronousstaticRAMs designed

to provide burstable, high-performance memory for commu-

nication and networking applications. The

IS61(64)LF12832A is organized as 131,072 words by 32

bits. The IS61(64)LF/VF12836A is organized as 131,072

words by 36 bits. The IS61(64)LF/VF25618A is organized

as 262,144 words by 18 bits. Fabricated with ISSI's

advanced CMOS technology, the device integrates a 2-bit

burst counter, high-speed SRAM core, and high-drive

capability outputs into a single monolithic circuit. All syn-

chronous inputs pass through registers controlled by a

positive-edge-triggered single clock input.

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

•

Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

• Snooze MODE for reduced-power standby

• Power Supply

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write

enable (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW) is

available for writing all bytes at one time, regardless of the

byte write controls.

LF: V^DD3.3V + 5%, VDDQ 3.3V/2.5V + 5%

VF: V^DD2.5V -5% +10%, VDDQ 2.5V -5% +10%

• JEDEC 100-Pin TQFP, 119-pin PBGA, and

165-pin PBGA packages

• Automotive temperature available

• Lead-free available

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address ad-

vance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-6.5

6.5

-7.5

7.5

Units

Clock Access Time

Cycle Time

tKC

7.5

8.5

Frequency

133

117

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00A

08/11/05

12 3 4 5 6 7...25

中文翻译

下载PDF

与IS64VF12832A相关器件

型号	品牌	获取价格	描述	数据表
IS64VF12832A-7.5TQLA3	ISSI	获取价格	128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS64VF12832EC-6.5B2A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64VF12832EC-6.5B2LA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64VF12832EC-6.5B3A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64VF12832EC-6.5B3LA3	ISSI	获取价格	Cache SRAM, 128KX32, 6.5ns, CMOS, PBGA165, TFBGA-165
IS64VF12832EC-6.5TQA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64VF12832EC-6.5TQLA3	ISSI	获取价格	Cache SRAM, 128KX32, 6.5ns, CMOS, PQFP100, TQFP-100
IS64VF12832EC-7.5B2A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64VF12832EC-7.5B2LA3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS64VF12832EC-7.5B3A3	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM

与IS64VF12832A相关文章

BSS138LT3G：一款高效能N沟道MOSFET的全面解析
2024-07-04

11
解读EGP10B二极管资料手册：产品特性、参数分析
2024-07-04

10
RT9164AGG手册资料详解：引脚信息、设计指南
2024-07-04

12
2SA1037KPT资料详解：产品特性、电气参数、设计指南
2024-07-04

15

产品中心

服务支持

精选活动

关于我们

帮助中心

IS64VF12832A

IS64VF12832A 数据手册

与IS64VF12832A相关器件

与IS64VF12832A相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS64VF12832A

IS64VF12832A 数据手册

与IS64VF12832A相关器件

与IS64VF12832A相关文章

您还可以找

您在本页遇到什么问题？