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IS61WV102416FBLL-10BLI PDF预览

IS61WV102416FBLL-10BLI

更新时间： 2024-02-26 21:09:49
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
19页 636K
描述
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, MINIBGA-48

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IS61WV102416FBLL-10BLI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TFBGA,Reach Compliance Code：compliant
HTS代码：8542.32.00.41Factory Lead Time：8 weeks
风险等级：5.66最长访问时间：10 ns
JESD-30 代码：R-PBGA-B48长度：8 mm
内存密度：16777216 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：48字数：1048576 words
字数代码：1000000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX16封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.4 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mmBase Number Matches：1

IS61WV102416FBLL-10BLI 数据手册

 浏览型号IS61WV102416FBLL-10BLI的Datasheet PDF文件第1页浏览型号IS61WV102416FBLL-10BLI的Datasheet PDF文件第2页浏览型号IS61WV102416FBLL-10BLI的Datasheet PDF文件第3页浏览型号IS61WV102416FBLL-10BLI的Datasheet PDF文件第5页浏览型号IS61WV102416FBLL-10BLI的Datasheet PDF文件第6页浏览型号IS61WV102416FBLL-10BLI的Datasheet PDF文件第7页 
IS61WV102416FALL  
IS61/64WV102416FBLL  
FUNCTION DESCRIPTION  
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM  
has three different modes supported. Each function is described below with Truth Table.  
STANDBY MODE  
Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high  
impedance state. CMOS input in this mode will maximize saving power.  
WRITE MODE  
Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O0-  
15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a  
byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified  
on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location.  
READ MODE  
Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output  
buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a  
byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from  
memory appears on I/O8-15.  
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as  
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.  
TRUTH TABLE  
Mode  
CS#  
WE#  
OE#  
LB#  
UB#  
I/O0-I/O7  
I/O8-I/O15  
VDD Current  
Not Selected  
H
L
L
L
L
L
L
L
L
X
H
X
H
H
H
L
X
H
X
L
X
L
X
X
H
H
L
High-Z  
High-Z  
High-Z  
DOUT  
High-Z  
DOUT  
DIN  
High-Z  
High-Z  
High-Z  
High-Z  
DOUT  
DOUT  
High-Z  
DIN  
ISB1, ISB2  
Output Disabled  
ICC,ICC1  
H
L
Read  
L
H
L
ICC,ICC1  
L
L
X
X
X
L
H
L
Write  
L
H
L
High-Z  
DIN  
ICC,ICC1  
L
L
DIN  
Note:  
1. CS# = H means CS1#=HIGH, and CS2= LOW in Dual Chip Select Device.  
Integrated Silicon Solution, Inc.- www.issi.com  
4
Rev. 0A  
12/13/2016  
1234567...19

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