Datasheet > IS61VF204818A-6.5B3I

IS61VF204818A-6.5B3I

更新时间： 2024-11-20 05:39:35

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
20页	330K
描述
36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

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中文翻译

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IS61LF102436A IS61VF102436A

IS61LF204818A IS61VF204818A

1M x 36, 2M x 18

36Mb SYNCHRONOUS FLOW-THROUGH

STATIC RAM

APRIL 2008

FEATURES

DESCRIPTION

The ISSI IS61LF/VF102436A and IS61LF/VF204818A

are high-speed, low-power synchronous static RAMs de-

signed to provide burstable, high-performance memory for

communication and networking applications.The IS61LF/

VF102436Aꢀisꢀorganizedꢀasꢀ1,048,476ꢀwordsꢀbyꢀ36ꢀbits.ꢀ

The IS61LF/VF204818Aꢀisꢀorganizedꢀasꢀ2M-wordsꢀbyꢀ18ꢀ

bits. Fabricated with ISSI'sꢀadvancedꢀCMOSꢀtechnology,ꢀ

the device integrates a 2-bit burst counter, high-speed

SRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀ

monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single

clock input.

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ

control

•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ

•ꢀ Three chip enable option for simple depth expan-

sion and address pipelining

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ AutoꢀPower-downꢀduringꢀdeselect

•ꢀ Singleꢀcycleꢀdeselect

Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀtheꢀ

risingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀoneꢀtoꢀ

four bytes wide as controlled by the write control inputs.

•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby

•ꢀ PowerꢀSupply

Separate byte enables allow individual bytes to be written.

Byteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀbyteꢀwriteꢀen-

able (BWE) input combined with one or more individual

byte write signals (BWx). Inꢀaddition,ꢀGlobalꢀWriteꢀ(GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

LF: V^{d d}3.3V + 5%, Vd d q 3.3V/2.5V + 5%

VF: V^{d d}2.5V + 5%, Vd d q 2.5V + 5%

•ꢀ JEDECꢀ100-PinꢀTQFPꢀandꢀ165-pinꢀPBGAꢀpack-

ages.

BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSP (Address Status

Processor)ꢀorꢀADSC (Address Status Cache Controller)

inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-

ated internally and controlled by the ADV (burst address

advance) input pin.

•ꢀ Lead-freeꢀavailable

Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀorder,ꢀ

LinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀInter-

leaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀorꢀleftꢀ

ﬂoating.

FAST ACCESS TIME

Symbol

Parameter

-6.5

6.5ꢀ

7.5ꢀ

133ꢀ

-7.5

7.5ꢀ

8.5ꢀ

117ꢀ

Units

tk q

t^{k c}

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

ꢀ

Frequencyꢀ

MHz

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device speciﬁcation before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc.

Rev. B

04/17/08

12 3 4 5 6 7...20

中文翻译

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与IS61VF204818A-6.5B3I相关器件

型号	品牌	获取价格	描述	数据表
IS61VF204818A-6.5TQ	ISSI	获取价格	36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204818A-6.5TQI	ISSI	获取价格	36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204818A-7.5B3	ISSI	获取价格	36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204818A-7.5B3I	ISSI	获取价格	36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204818A-7.5TQ	ISSI	获取价格	36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204818A-7.5TQI	ISSI	获取价格	36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204818B-7.5TQLI	ISSI	获取价格	Cache SRAM, 2MX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
IS61VF204836B-6.5B2	ISSI	获取价格	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204836B-6.5B2L	ISSI	获取价格	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204836B-6.5B2LI	ISSI	获取价格	Cache SRAM, 2MX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-02

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