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IS61VF204818A-7.5B3 PDF预览

IS61VF204818A-7.5B3

更新时间： 2024-11-20 05:39:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
20页 330K
描述
36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

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中文翻译

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IS61VF204818A-7.5B3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：TBGA, BGA165,11X15,40针数：165
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
Is Samacsys：N最长访问时间：7.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：117 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：37748736 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端子数量：165字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.14 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.34 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

IS61VF204818A-7.5B3 数据手册

 浏览型号IS61VF204818A-7.5B3的Datasheet PDF文件第2页浏览型号IS61VF204818A-7.5B3的Datasheet PDF文件第3页浏览型号IS61VF204818A-7.5B3的Datasheet PDF文件第4页浏览型号IS61VF204818A-7.5B3的Datasheet PDF文件第5页浏览型号IS61VF204818A-7.5B3的Datasheet PDF文件第6页浏览型号IS61VF204818A-7.5B3的Datasheet PDF文件第7页 
IS61LF102436A IS61VF102436A  
IS61LF204818A IS61VF204818A  
1M x 36, 2M x 18  
36Mb SYNCHRONOUS FLOW-THROUGH  
STATIC RAM  
APRIL 2008  
FEATURES  
DESCRIPTION  
The ISSI IS61LF/VF102436A and IS61LF/VF204818A  
are high-speed, low-power synchronous static RAMs de-  
signed to provide burstable, high-performance memory for  
communication and networking applications.The IS61LF/  
VF102436Aꢀisꢀorganizedꢀasꢀ1,048,476ꢀwordsꢀbyꢀ36ꢀbits.ꢀ  
The IS61LF/VF204818Aꢀisꢀorganizedꢀasꢀ2M-wordsꢀbyꢀ18ꢀ  
bits. Fabricated with ISSI'sꢀadvancedꢀCMOSꢀtechnology,ꢀ  
the device integrates a 2-bit burst counter, high-speed  
SRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀ  
monolithic circuit. All synchronous inputs pass through  
registers controlled by a positive-edge-triggered single  
clock input.  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ  
control  
•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ  
•ꢀ Three chip enable option for simple depth expan-  
sion and address pipelining  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ AutoꢀPower-downꢀduringꢀdeselect  
•ꢀ Singleꢀcycleꢀdeselect  
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀtheꢀ  
risingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀoneꢀtoꢀ  
four bytes wide as controlled by the write control inputs.  
•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby  
•ꢀ PowerꢀSupply  
Separate byte enables allow individual bytes to be written.  
Byteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀbyteꢀwriteꢀen-  
able (BWE) input combined with one or more individual  
byte write signals (BWx). Inꢀaddition,ꢀGlobalꢀWriteꢀ(GW)  
is available for writing all bytes at one time, regardless of  
the byte write controls.  
LF: Vd d 3.3V + 5%, Vd d q 3.3V/2.5V + 5%  
VF: Vd d 2.5V + 5%, Vd d q 2.5V + 5%  
•ꢀ JEDECꢀ100-PinꢀTQFPꢀandꢀ165-pinꢀPBGAꢀpack-  
ages.  
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSP (Address Status  
Processor)ꢀorꢀADSC (Address Status Cache Controller)  
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-  
ated internally and controlled by the ADV (burst address  
advance) input pin.  
•ꢀ Lead-freeꢀavailable  
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀorder,ꢀ  
LinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀInter-  
leaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀorꢀleftꢀ  
floating.  
FAST ACCESS TIME  
Symbol  
Parameter  
-6.5  
6.5ꢀ  
7.5ꢀ  
133ꢀ  
-7.5  
7.5ꢀ  
8.5ꢀ  
117ꢀ  
Units  
ns  
tk q  
tk c  
ꢀ
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
ns  
ꢀ
Frequencyꢀ  
MHz  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-  
est version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc.  
1
Rev. B  
04/17/08  
1234567...20

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与IS61VF204818A-7.5B3相关器件

型号 品牌 获取价格 描述 数据表
IS61VF204818A-7.5B3I ISSI

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 		36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204818A-7.5TQ ISSI

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 		36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204818A-7.5TQI ISSI

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 		36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204818B-7.5TQLI ISSI

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 		Cache SRAM, 2MX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
IS61VF204836B-6.5B2 ISSI

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 		2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204836B-6.5B2L ISSI

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 		2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204836B-6.5B2LI ISSI

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 		Cache SRAM, 2MX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-02
IS61VF204836B-6.5B3 ISSI

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 		2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204836B-6.5B3L ISSI

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 		2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF204836B-6.5B3LI ISSI

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 		Cache SRAM, 2MX36, 6.5ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, LEAD FREE, PLASTIC, TFBGA

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