5秒后页面跳转
捷配首页

Datasheet > IS61SP12836-166TQI
IS61SP12836-166TQI PDF预览

IS61SP12836-166TQI

更新时间： 2024-11-23 15:35:31
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
17页 118K
描述
Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, TQFP-100

阅读下载

中文翻译

获取价格

IS61SP12836-166TQI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.88
最长访问时间：3.5 ns最大时钟频率 (fCLK)：166 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：4718592 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.02 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.3 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

IS61SP12836-166TQI 数据手册

 浏览型号IS61SP12836-166TQI的Datasheet PDF文件第2页浏览型号IS61SP12836-166TQI的Datasheet PDF文件第3页浏览型号IS61SP12836-166TQI的Datasheet PDF文件第4页浏览型号IS61SP12836-166TQI的Datasheet PDF文件第5页浏览型号IS61SP12836-166TQI的Datasheet PDF文件第6页浏览型号IS61SP12836-166TQI的Datasheet PDF文件第7页 
®
IS61SP12832  
IS61SP12836  
128K x 32, 128K x 36 SYNCHRONOUS  
PIPELINED STATIC RAM  
ISSI  
FEBRUARY 2004  
FEATURES  
DESCRIPTION  
The ISSI IS61SP12832 and IS61SP12836 are high-speed  
synchronous static RAM designed to provide a burstable,  
high-performance memory for high speed networking and  
communication applications. It is organized as 131,072  
words by 32 bits and 36 bits, fabricated with ISSI's ad-  
vanced CMOS technology. The device integrates a 2-bit  
burst counter, high-speed SRAM core, and high-drive  
capability outputs into a single monolithic circuit. All syn-  
chronous inputs pass through registers controlled by a  
positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control using  
MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
• Common data inputs and data outputs  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be from  
one to four bytes wide as controlled by the write control  
inputs.  
• JEDEC 100-Pin TQFP and  
119-pin PBGA packages  
• Single +3.3V, +10%, –5% power supply  
• Power-down snooze mode  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQa, BW2 controls DQb, BW3 controls  
DQc, BW4 controls DQd, conditioned by BWE being  
LOW. A LOW on GW input would cause all bytes to be  
written.  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-166  
3.5  
6
-133  
4
-5  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
7.5  
133  
10  
100  
ns  
Frequency  
166  
MHz  
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. B  
1
02/11/04  
1234567...17

中文翻译

下载PDF

与IS61SP12836-166TQI相关器件

型号 品牌 获取价格 描述 数据表
IS61SP12836-200B ISSI

获取价格

 		Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61SP12836-200TQ ISSI

获取价格

 		Cache SRAM, 128KX36, 3.1ns, CMOS, PQFP100, TQFP-100
IS61SP12836-3.5B ETC

获取价格

 		x36 Fast Synchronous SRAM
IS61SP12836-3.5TQ ETC

获取价格

 		x36 Fast Synchronous SRAM
IS61SP12836-3.8B ETC

获取价格

 		x36 Fast Synchronous SRAM
IS61SP12836-3.8TQ ETC

获取价格

 		x36 Fast Synchronous SRAM
IS61SP12836-3.8TQI ETC

获取价格

 		x36 Fast Synchronous SRAM
IS61SP12836-5B ICSI

获取价格

 		128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-5TQ ICSI

获取价格

 		128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-5TQ ISSI

获取价格

 		Cache SRAM, 128KX36, 5ns, CMOS, PQFP100, TQFP-100

与IS61SP12836-166TQI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证